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LT3669

IO-Link Transceiver with Integrated Step-Down Regulator and LDO

Linear Technology 

LT3669/LT3669-2

APPLICATIONS INFORMATION

±2kV (Level 2) surge and ±6kV (Level 3) contact/air

discharge events provided that there are bypass capacitors

(>470pF) attached to pins CQ1 and Q2 and L+. For IO-Link

L+ operation up to 30V, use SM6T36A or equivalent TVS

clamps to further increase surge and ESD protection. Use

SMCJ36A or equivalent TVS clamps for L+ operation above

36V. Figure 22 shows the placement of the TVS diodes to

protect the LT3669 against surge events applied between

any combination of the line driver ports.

UNDERVOLTAGE LOCKOUT

The LT3669 undervoltage lockout circuitry monitors the

input supply L+ as well as the input pin EN/UVLO and

disables the internal circuitry if various conditions are

not met.

The LT3669 EN/UVLO pin voltage is internally compared

to a precise 1.5V reference and can be used as an adjust-

able undervoltage lockout (see Figure 23). Setting this pin

below the 1.5V threshold disables the switcher, LDO and

line drivers. Typically, UVLO is used in situations in which

the input supply is current limited, or has a relatively high

source resistance. A switching regulator draws constant

power from the source, so source current increases as

source voltage drops. This looks like a negative resistance

load to the source and can cause the source to current

limit or latch low under low source voltage conditions.

EN/UVLO prevents the LT3669 from operating at source

voltages where the problems might occur.

Additional circuitry monitors the L+ voltage, too, and dis-

ables the line drivers if it falls below 6.5V. The switching

regulator and LDO are disabled for VL+ below 6.0V. Current

is drawn from L+ as soon as it is above 0.65V. Setting

EN/UVLO low reduces the quiescent current to 1.15mA.

Keep the connections from the resistors to the EN/UVLO

pin short and ensure the interplane or surface capacitance

to switching nodes is minimized. If high resistor values

are used, bypass the EN/UVLO pin with a 1nF capacitor to

prevent coupling problems from the switch node.

OUTPUT VOLTAGE MONITORING

The LT3669 provides power supply monitoring for

microprocessor-based systems including a power-on

reset (POR).

A precise internal voltage reference and precision POR

comparator circuit monitor the LT3669 LDO and switch-

ing regulator output voltages. These output voltages must

be above 92.7% of the programmed value for RST not to

be asserted (refer to the Timing Diagrams section). The

LT3669 will assert RST during power-up, power-down

and brownout conditions. Once the output voltage rises

above the RST threshold, the adjustable reset timer is

started and RST is released after the reset timeout period

L+

LT3669/

LT3669-2

CQ1

Q2

GND

36692 F22

Figure 22. Placement of TVS Diodes

VL+

R5

C3

R6

LT3669/LT3669-2

EN/UVLO

+

–

INTERNAL

ENABLE

+– 1.5V

AGND

GND

36692 F23

Figure 23. Undervoltage Lockout

3669fa

34

For more information www.linear.com/LT3669

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