AD9361 データシートの表示（PDF） - Analog Devices

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AD9361

RF Agile Transceiver

Analog Devices 

Data Sheet

AD9361

Pin No.

J11

Type1 Mnemonic

I/O

P1_D3/RX_D1_P

J12

I/O

P1_D1/RX_D0_P

K1, L1

K3

K4

K5

K6

K7

I

RX1C_P, RX1C_N

I

VDDA1P3_TX_SYNTH

I

VDDA1P3_BB

I

RESETB

I

SPI_ENB

I/O

P1_D8/RX_D4_N

K8

I/O

P1_D6/RX_D3_N

K9

I/O

P1_D4/RX_D2_N

K10

I/O

P1_D2/RX_D1_N

K11

I/O

P1_D0/RX_D0_N

L4

I

L5

I

L6

O

M1, M2

I

M5

I

M7, M8

O

M9, M10

O

M11, M12

I

RBIAS

AUXADC

SPI_DO

RX1A_P, RX1A_N

TX_MON1

TX1A_P, TX1A_N

TX1B_P, TX1B_N

XTALP, XTALN

1 I is input, O is output, I/O is input/output, or NC is not connected.

Description

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D1_P) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Receive Channel 1 Differential Input C. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Tie unused pins to ground.

1.3 V Supply Input.

1.3 V Supply Input.

Asynchronous Reset. Logic low resets the device.

SPI Enable Input. Set this pin to logic low to enable the SPI bus.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit RX

differential output bus with internal LVDS termination.

Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor

to ground.

Auxiliary ADC Input. If this pin is unused, tie it to ground.

SPI Serial Data Output in 4-Wire Mode, or High-Z in 3-Wire Mode.

Receive Channel 1 Differential Input A. Alternatively, each pin can be used as a

single-ended input. Tie unused pins to ground.

Transmit Channel 1 Power Monitor Input. When this pin is unused, tie it to ground.

Transmit Channel 1 Differential Output A. Tie unused pins to 1.3 V.

Transmit Channel 1 Differential Output B. Tie unused pins to 1.3 V.

Reference Frequency Crystal Connections. When a crystal is used, connect it

between these two pins. When an external clock source is used, connect it to

XTALN and leave XTALP unconnected.

Rev. F | Page 19 of 36

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