EVAL-AD7450ACB データシートの表示（PDF） - Analog Devices

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EVAL-AD7450ACB

Differential Input, 1 MSPS 10-Bit and 12-Bit ADCs in an 8-Lead SOT-23

Analog Devices 

CIRCUIT INFORMATION

The AD7440/AD7450A are 10-bit and 12-bit fast, low power,

single-supply, successive approximation analog-to-digital

converters (ADCs). They can operate with a 5 V or 3 V power

supply and are capable of throughput rates up to 1 MSPS when

supplied with an 18 MHz SCLK. They require an external

reference to be applied to the VREF pin, with the value of the

reference chosen depending on the power supply and what suits

the application.

When they are operated with a 5 V supply, the maximum

reference that can be applied is 3.5 V. When they are operated

with a 3 V supply, the maximum reference that can be applied is

2.2 V (see the Reference section).

The AD7440/AD7450A have an on-chip differential track-and-

hold amplifier, a successive approximation (SAR) ADC, and a

serial interface housed in either an 8-lead SOT-23 or an MSOP

package. The serial clock input accesses data from the part and

provides the clock source for the successive approximation

ADC. The AD7440/AD7450A feature a power-down option for

reduced power consumption between conversions. The power-

down feature is implemented across the standard serial interface

as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7440/AD7450A are successive approximation ADCs

based around two capacitive DACs. Figure 23 and Figure 24

show simplified schematics of the ADC in acquisition and

conversion phase, respectively. The ADC is comprised of

control logic, an SAR, and two capacitive DACs. In Figure 23

(acquisition phase), SW3 is closed, SW1 and SW2 are in

Position A, the comparator is held in a balanced condition,

and the sampling capacitor arrays acquire the differential

signal on the input.

CAPACITIVE

DAC

VIN+

VIN–

B

CS

A

SW1

A

SW2

B

CS

VREF

SW3

CONTROL

LOGIC

COMPARATOR

CAPACITIVE

DAC

Figure 23. ADC Acquisition Phase

AD7440/AD7450A

When the ADC starts a conversion (Figure 24), SW3 opens and

SW1 and SW2 move to Position B, causing the comparator to

become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistri-

bution DACs are used to add and subtract fixed amounts of

charge from the sampling capacitor arrays to bring the compar-

ator back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC’s output code. The output impedances of the

sources driving the VIN+ and the VIN– pins must be matched;

otherwise, the two inputs have different settling times, resulting

in errors.

CAPACITIVE

DAC

VIN+

VIN–

B

CS

A

SW1

A

SW2

B

CS

VREF

SW3

CONTROL

LOGIC

COMPARATOR

CAPACITIVE

DAC

Figure 24. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7440/AD7450A is twos

complement. The designed code transitions occur at successive

LSB values (1 LSB, 2 LSBs, and so on). The LSB size of the

AD7450A is 2 × VREF/4096, and the LSB size of the AD7440 is

2 × VREF/1024. The ideal transfer characteristic of the

AD7440/AD7450A is shown in Figure 25.

011...111

011...110

1LSB

1LSB

=

=

22××VVRREEFF//41009264

AD7450A

AD7440

000...001

000...000

111...111

100...010

100...001

100...000

–VREF1 LSB

0 LSB

+VREF – 1 LSB

ANALOG INPUT

(VIN+ – VIN–)

Figure 25. AD7440/AD7450A Ideal Transfer Characteristic

Rev. C | Page 15 of 28

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