AD7451 データシートの表示（PDF） - Analog Devices

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AD7451

Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23

Analog Devices 

THEORY OF OPERATION

CIRCUIT INFORMATION

The AD7441/AD7451 are 10-/12-bit, high speed, low power,

single-supply, successive approximation, analog-to-digital con-

verters (ADCs) with a pseudo differential analog input. These

parts operate with a single 2.7 V to 5.25 V power supply and are

capable of throughput rates up to 1 MSPS when supplied with

an 18 MHz SCLK. The AD7441/AD7451 require an external

reference to be applied to the VREF pin.

The AD7441/AD7451 have a SAR ADC, an on-chip differential

track-and-hold amplifier, and a serial interface housed in either

an 8-lead SOT-23 or an MSOP package. The serial clock input

accesses data from the part and provides the clock source for

the SAR ADC. The AD7441/AD7451 feature a power-down

option for reduced power consumption between conversions.

The power-down feature is implemented across the standard

serial interface, as described in the Modes of Operation section.

CONVERTER OPERATION

The AD7441/AD7451 are SAR ADCs based around two

capacitive DACs. Figure 19 and Figure 20 show simplified

schematics of the ADC in the acquisition and conversion phase,

respectively. The ADC is comprised of control logic, an SAR,

and two capacitive DACs. In Figure 19 (acquisition phase), SW3

is closed, SW1 and SW2 are in Position A, the comparator is

held in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

CAPACITIVE

DAC

VIN+

VIN–

B

CS

A

SW1

A

SW2

B

VREF

CS

SW3

CONTROL

LOGIC

COMPARATOR

CAPACITIVE

DAC

Figure 19. ADC Acquisition Phase

AD7441/AD7451

When the ADC starts a conversion (see Figure 20), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribu-

tion DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is rebal-

anced, the conversion is complete. The control logic generates

the ADC output code. The output impedances of the sources

driving the VIN+ and VIN– pins must be matched; otherwise the

two inputs have different settling times, resulting in errors.

CAPACITIVE

DAC

VIN+

VIN–

B

CS

A

SW1

A

SW2

B VREF CS

SW3

CONTROL

LOGIC

COMPARATOR

CAPACITIVE

DAC

Figure 20. ADC Conversion Phase

ADC TRANSFER FUNCTION

The output coding for the AD7441/AD7451 is straight (natural)

binary. The designed code transitions occur at successive LSB

values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451

is VREF/4096, and the LSB size of the AD7441 is VREF/1024. The

ideal transfer characteristic of the AD7441/AD7451 is shown in

Figure 21.

111...111

111...110

1LSB = VREF/4096 (AD7451)

1LSB = VREF/1024 (AD7441)

111...000

011...111

000...010

000...001

000...000

0V 1LSB

VREF – 1LSB

ANALOG INPUT

Figure 21. AD7441/AD7451 Ideal Transfer Characteristic

Rev. D | Page 13 of 24

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