AD8117 データシートの表示（PDF） - Analog Devices

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AD8117

600 MHz, 32 × 32 Buffered, Analog Crosspoint Switch

Analog Devices 

Data Sheet

AD8117/AD8118

TRUTH TABLE AND LOGIC DIAGRAM

Table 9. Operation Truth Table

WE UPDATE CLK Data Input

XX

X

X

Data Output

X

0X

X

D0…D51 Not applicable in parallel mode

1X

Datai2

Datai-192

0X

10

1X

X

D0…D51 Not applicable in parallel mode

A0…A43

X

X

Not applicable in parallel mode

X

X

X

RESET

0

1

1

1

1

1

SER/PAR

X

0

0

1

X

1

Operation/Comment

Asynchronous reset. All outputs are

disabled. Remainder of logic in 192-bit

shift register is unchanged.

Broadcast. The data on parallel lines D0

to D5 are loaded into all 32 output address

locations of the 192-bit shift register.

Serial mode. The data on the serial DATA

IN line is loaded into the serial register.

The first bit clocked into the serial register

appears at DATA OUT 192 clock cycles

later.

Parallel programming mode. The data

on parallel lines D0 to D5 are loaded into

the shift register location addressed by

A0 to A4.

Switch matrix update. Data in the 192-

bit shift register transfers into the parallel

latches that control the switch array.

No change in logic.

1 D0…D5: data bits.

2 Datai: serial data.

3 A0…A4: address bits.

Rev. B | Page 13 of 36

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