SC14480A2M6XXXXVE データシートの表示（PDF） - Unspecified

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SC14480A2M6XXXXVE

1.8V Single Chip for DECT

Unspecified 

XTAL1

10.368 MHz

20.736 MHz

XTAL2

Oscilator

RFCLK <RFEN, RFDIS>

BXTAL_DIV (ES5) <RFEN, RFDIS>

XTAL_DIV (ES1-4) BXTAL_EN[1]

/2 1

BXTAL_EN[0]

0

XTAL_DIV

/2 1

0

external_BB testmode

1

0

MODE20M

0

/2 1

P2_7_MODE

ADCDIG (RF)

PLLDIG (RF)

Port P2[7]

/2

BXTAL pin

RFCU clock

(full rate)

Demodulator Core

(1/2 bit rate)

external_BB

testmode

165.888,

PLL_CLK_SEL DIV2_CLK_SEL

82.944,

0 = XTAL, 1 = PLL 0 = DIV2, 1 = DIV1

41.472 MHz

non-dynamic switching

OWI_DIV[1-0]

static

PLL

1

0

PLL/2 P2

DIV1_CLK

1

0 DIV2_CLK

OWI_SEL

P3 prescaler *)

CLK_DSP_EN

CLK_DSP_DIV[2-0]

dynamic

PLL_DIP_DIV

PLL/N P4

0

0

1 DIVN_CLK

PLL_CLK_SEL

/16

HCLK_DIV[2-0]

/1

dynamic

MEM_STROBE[2-0]

PCLK_DIV[1-0]

HCLK

dynamic

/16 P1 1 dynamic switching

P1

MCRAM1_EN

<U_PSC>

and PRESCALER=1

and XDIV=1

l P3 prescaler

tia Divide by 16: (PRESCALER=1 and <U_PSC>)

or HCLK_PRE=1

Divide by 1: (PRESCALER=0 or <U_INTx> or U_VNMI or U_VINT)

Confiden and HCLK_PRE=0

ramclk

SRAM1_EN

/2.25

/4.5

/9

4x1.152 MHz

2x1.152 MHz

1.152 MHz

<M_CON>

DIV1,2,4

DIV115200

CODEC_CLK_SEL <WNTP1, WNTM1>

1.152 MHz

CODEC_DIV[6-0] 2.304 MHz

4.608 MHz

1.152MHz

static

CLK_MAIN

CLK_CODEC_REG

Main

see

page

counter 56

4 kHz

8 kHz

16 kHz

DSP_MAIN_SYNC0_REG

DSP_MAIN_SYNC1_REG

DSP_MAIN_CTRL_REG 32 kHz

JTAG (OWI clock)

Gen2DSP

Pclk (APB)

PENABLE

CR16Cplus,

DMA, SDI

MCRAM_CLK

SRAM_CLK

DIP clock

Micro wire

DIP sequencer

BMC

CLK100(SLOTZERO)

CLK_PCM

CLK_DA_LSR

CLK_DA_PA

CLK_AD (MIC)

RAMOUT_SYNC[0-3]

RAMIN_SYNC[0-3]

DSP_SYNC[0-3]

DA_LSR_SYNC

DA_LSR_CLASSD_SYNC

AD_SYNC

ADC_SYNC, PCM_SYNC

January 5, 2009

PER_CLK_SEL

PER_DIV[6-0]

static

2.304 MHz

1.152 MHz

/10

/4

/8

static

115.2kHz

288kHz

144kHz

PER10_CLK_SEL

DIV

PER10_DIV[2-0]

10.368 MHz

CP_FREQ

cp_clk

/2

/2, /4, /8

PER20_DIV[2-0] 41.472 MHz for SPI = 20.736 MHz

SOC

Timers 0,1,2

Timers 0,1

ADC

Capture Timers

JTAG hot insert

Keyboard IF

10.2 ms

UART

ACCESS1

ACCESS2

CLASSD

Chargepump

trippler

SPI

Figure 5 SC14480A5M, A2M6 Clock divider overview

© 2008-2009 SiTel Semiconductor

19

Version: January 21, 2009 v1.0

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