AD9142A データシートの表示（PDF） - Analog Devices

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AD9142A

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

Data Sheet

Interrupt Select1 Register...........................................................54

Frame Mode Register..................................................................54

Data Control 0 Register..............................................................55

Data Control 1 Register..............................................................55

Data Control 2 Register..............................................................55

Data Control 3 Register..............................................................55

Data Status 0 Register .................................................................55

DAC Clock Receiver Control Register .....................................56

Ref Clock Receiver Control Register ........................................56

PLL Control 0 Register ...............................................................56

PLL Control 2 Register ...............................................................57

PLL Control 3 Register ...............................................................57

PLL Status 0 Register ..................................................................57

PLL Status 1 Register ..................................................................58

IDAC FS Adjust LSB Register....................................................58

IDAC FS Adjust MSB Register ..................................................58

QDAC FS Adjust LSB Register ..................................................58

QDAC FS Adjust MSB Register ................................................58

Die Temperature Sensor Control Register...............................59

Die Temperature LSB Register ..................................................59

Die Temperature MSB Register.................................................59

Chip ID Register..........................................................................59

Interrupt Configuation Register ...............................................59

Sync Control Register .................................................................60

Frame Reset Control Register....................................................60

FIFO Level Configuration Register ..........................................60

FIFO Level Readback Register ..................................................61

FIFO Control Register................................................................61

Data Format Select Register.......................................................61

Datapath Control Register .........................................................61

Interpolation Control Register ..................................................62

Over Threshold Control 0 Register ..........................................62

Over Threshold Control 1 Register ..........................................62

Over Threshold Control 2 Register ..........................................62

Input Power Readback LSB Register ........................................62

Input Power Readback MSB Register.......................................63

NCO Control Register................................................................63

NCO Frequency Tuning Word 0 Register ...............................63

NCO Frequency Tuning Word 1 Register ...............................63

NCO Frequency Tuning Word 2 Register ...............................63

AD9142A

NCO Frequency Tuning Word 3 Register ...............................64

NCO Phase Offset 0 Register ....................................................64

NCO Phase Offset 1 Register ....................................................64

IQ Phase Adjust 0 Register ........................................................64

IQ Phase Adjust 1 Register ........................................................64

Power Down Data Input 0 Register..........................................65

IDAC DC Offset 0 Register .......................................................65

IDAC DC Offset 1 Register .......................................................65

QDAC DC Offset 0 Register......................................................65

QDAC DC Offset 1 Register......................................................65

IDAC Gain Adjust Register .......................................................65

QDAC Gain Adjust Register......................................................66

Gain Step Control 0 Register.....................................................66

Gain Step Control 1 Register.....................................................66

Tx Enable Control Register .......................................................66

DAC Output Control Register ..................................................67

DLL Cell Enable 0 Register........................................................67

DLL Cell Enable 1 Register........................................................67

SED Control Register .................................................................67

SED Pattern I0 Low Bits Register..............................................68

SED Pattern I0 High Bits Register ............................................68

SED Pattern Q0 Low Bits Register............................................68

SED Pattern Q0 High Bits Register ..........................................68

SED Pattern I1 Low Bits Register..............................................68

SED Pattern I1 High Bits Register ............................................68

SED Pattern Q1 Low Bits Register............................................68

SED Pattern Q1 High Bits Register ..........................................69

Parity Control Register...............................................................69

Parity Error Rising Edge Register .............................................69

Parity Error Falling Edge Register ............................................69

Version Register ..........................................................................69

DAC Latency and System Skews...................................................70

DAC Latency Variations.............................................................70

FIFO Latency Variation..............................................................70

Clock Generation Latency Variation........................................71

Correcting System Skews...........................................................71

Packaging and Ordering Information ..........................................72

Outline Dimensions ...................................................................72

Ordering Guide ...........................................................................72

Rev. A | Page 3 of 72

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