S3C6410 データシートの表示（PDF） - Samsung
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S3C6410 Datasheet PDF : 1378 Pages
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Table of Contents (Continued)
Chapter 11 DMA Controller
11.1 Overview ............................................................................................................................................... 11-1
11.2 Features ................................................................................................................................................ 11-2
11.3 block diagram........................................................................................................................................ 11-3
11.4 DMA sources......................................................................................................................................... 11-4
11.5 DMA interface ....................................................................................................................................... 11-5
11.5.1 DMA request signals ..................................................................................................................... 111-5
11.5.2 DMA response signals................................................................................................................... 11-5
11.5.3 Transfer types................................................................................................................................ 11-5
11.5.3.1 Peripheral-to-memory transaction under DMA controller flow control ................................... 11-6
11.5.3.2 Memory-to- Peripheral transaction under DMA controller flow control .................................. 11-6
11.5.3.3 Memory-to-memory transaction under DMA controller flow control ...................................... 11-6
11.5.3.4 Peripheral-to-peripheral transaction under DMA controller flow control ................................ 11-7
11.5.4 Signal timing .................................................................................................................................. 11-8
11.6 Functional timing diagram..................................................................................................................... 11-9
11.7 Programmer's model............................................................................................................................. 11-9
11.7.1 Programming the DMA controller .................................................................................................. 11-9
11.7.2 Enabling the DMA controller.......................................................................................................... 11-9
11.7.3 Disabling the DMA controller ......................................................................................................... 11-9
11.7.4 Enabling a DMA channel ............................................................................................................... 11-9
11.7.5 Disabling a DMA channel .............................................................................................................. 11-10
11.7.5.1 Disabling a DMA channel and losing data in the FIFO: ......................................................... 11-10
11.7.5.2 Disabling a DMA channel without losing data in the FIFO:.................................................... 11-10
11.7.6 Set up a new DMA transfer .........................htt.p://ww.w.Da.taShe.et4U..net/ ............................................................................. 11-10
11.7.7 Halting a DMA channel.................................................................................................................. 11-10
11.7.8 Programming a DMA channel ....................................................................................................... 11-11
11.8 Register Description.............................................................................................................................. 11-12
11.8.1 DMA register location .................................................................................................................... 11-12
11.8.2 Interrupt status register, DMACIntStatus....................................................................................... 11-15
11.8.3 Interrupt terminal count status register, DMACIntTCStatus .......................................................... 11-15
11.8.4 Interrupt terminal count clear register, DMACIntTCClear ............................................................. 11-15
11.8.5 Interrupt error status register, DMACIntErrorStatus...................................................................... 11-16
11.8.6 Interrupt error clear register, DMACIntErrClr................................................................................. 11-16
11.8.7 Raw interrupt terminal counter status register, DMACRawIntTCStatus ....................................... 11-16
11.8.8 Raw error interrupt status register, DMACRawIntErrorStatus ...................................................... 11-17
11.8.9 Enable channel register, DMACEnbldChns .................................................................................. 11-17
11.8.10 Software burst request register, DMACSoftBReq ....................................................................... 11-17
11.8.11 Software single request register, DMACSoftSReq...................................................................... 11-18
11.8.14 Configuration register, DMACConfiguration ................................................................................ 11-19
11.8.15 Synchronization register, DMACSync ......................................................................................... 11-19
11.8.16 Channel source address register, DMACCxSrcAddr .................................................................. 11-20
11.8.17 Channel destination address register, DMACCxDestAddr ......................................................... 11-20
11.8.18 Channel linked list item register, DMACCxLLI ............................................................................ 11-21
11.8.19 Channel control register, DMACCxControl0................................................................................ 11-21
11.8.20 Channel control register, DMACCxControl1................................................................................ 11-24
11.8.21 Channel configuration register, DMACCxConfiguration.............................................................. 11-25
11.8.22 Channel configuration expansion register, DMACCxConfigurationExp ...................................... 11-27
S3C6410X_USER’S MANUAL_REV 1.10
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datasheet pdf - http://www.DataSheet4U.net/
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