S3C6410 データシートの表示（PDF） - Samsung
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S3C6410 Datasheet PDF : 1378 Pages
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Table of Contents (Continued)
Chapter 21 Multi-FORMAT Video Codec
21.4.2 Frame buffer...................................................................................................................................21-12
21.4.3 Rotation/Mirroring ..........................................................................................................................21-14
21.4.3.1 PrP rotator module..................................................................................................................21-14
21.4.3.2 PP rotator module...................................................................................................................21-15
21.4.3.3 Rotation/mirroring modes .......................................................................................................21-15
21.4.4 Motion Estimation...........................................................................................................................21-17
21.4.4.1 ME DMA block ........................................................................................................................21-19
21.4.5 Inter-Prediction...............................................................................................................................21-20
21.4.6 Intra-Prediction...............................................................................................................................21-22
21.4.7 Transform/Quantization .................................................................................................................21-24
21.4.7.1 Overview.................................................................................................................................21-24
21.4.7.2 Block diagram .........................................................................................................................21-24
21.4.7.3 MPEG-4/H.263 .......................................................................................................................21-25
121.4.7.4 H.264 ....................................................................................................................................21-26
21.4.8 Overlap-smoothing/Deblocking Filter.............................................................................................21-27
21.4.8.1 Overview.................................................................................................................................21-27
21.4.8.2 Processing modes ..................................................................................................................21-27
21.4.8.3 Block diagram .........................................................................................................................21-29
21.4.8.4 H.264 Deblocking filter ...........................................................................................................21-30
21.4.8.5 H.263 Annex J Deblocking filter .............................................................................................21-30
21.4.8.6 VC-1 Overlap-smoothing filter ................................................................................................21-30
21.4.8.7 VC-1 Deblocking filter .................................................................................................................21-30
21.4.8.8 MPEG-4 Deblocking filter for post-processing http://www.DataSheet4U.net/ .......................................................................21-31
21.4.9 Coefficient Buffer Interface ............................................................................................................21-31
21.4.9.1 Block diagram .........................................................................................................................21-31
21.4.9.2 Reordering coefficients...........................................................................................................21-32
21.4.9.3 Accessing the coefficient memory..........................................................................................21-32
21.4.9.4 Encoder operation ..................................................................................................................21-33
21.4.9.5 Decoder operation ..................................................................................................................21-34
21.4.10 Macroblock Controller ..................................................................................................................21-35
21.5 FIMV-MFC V1.0 Programming Model (Special Function Register ) .....................................................21-36
21.5.1 BIT Processor operations ..............................................................................................................21-37
21.5.1.1 Description of BIT Processor Registers .................................................................................21-37
21.5.1.2 BIT Processor Code Download ..............................................................................................21-37
21.5.1.3 Bit Stream Buffer management ..............................................................................................21-38
21.5.1.4 Description of Run Commands ..............................................................................................21-39
21.5.1.5 Parameter Buffer Management ..............................................................................................21-43
21.5.1.6 Working Buffer Management..................................................................................................21-44
21.5.1.7 Description of Run Process ....................................................................................................21-47
21.5.1.8 Description of Pre/Post Rotation ............................................................................................21-47
21.5.1.9 Sample operation flows ..........................................................................................................21-49
21.5.2 The host interface registers ...........................................................................................................21-52
21.5.2.1 Summary of host interface registers.......................................................................................21-53
21.5.2.2 Detailed Description of BIT Processor Registers ...................................................................21-61
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S3C6410X_USER’S MANUAL_REV 1.00
datasheet pdf - http://www.DataSheet4U.net/
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