ST24LC21B, ST24LW21, ST24FC21, ST24FW21
Figure 5. Error Recovery Mechanism Flowchart for the ST24FC21 and ST24FW21 products
Transition
State
(VESA 2)
Memory Power On
Internal Address Pointer = 0
VCLK YES
NO
NO SCL
YES
SDA Hi-Z
VCLK Internal Counter = 0
Start Internal 2 sec Timer
Send Data bit (MSB first) pointed
by the Address Pointer and
auto-increment pointed bit/byte
Transmit-Only Mode
(DDC1)
SCL YES
NO
Valid
I2C access
(START + Device Select)
?
YES
Reset VCLK Internal Counter
and Reset Internal Timer
NO VCLK
YES
Increment VCLK Counter
NO
Counter = 128
or Timer > 2 sec
YES
Switch Back to
Transmit-Only Mode
I2C communication idle
waiting for a Device Select byte
Reset Counter and Timer
Send Acknowledge
Respond to the Incoming
I2C Command
AI01748
I2C Mode
(DDC2B)
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