MT46V16M8TG-8 データシートの表示（PDF） - Micron Technology

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MT46V16M8TG-8

DOUBLE DATA RATE (DDR) SDRAM

Micron Technology 

EXTENDED MODE REGISTER

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable, output

drive strength, and QFC#. These functions are con-

trolled via the bits shown in Figure 3. The extended

mode register is programmed via the LOAD MODE

REGISTER command to the mode register (with

BA0 = 1 and BA1 = 0) and will retain the stored informa-

tion until it is programmed again or the device loses

power. The enabling of the DLL should always be

followed by a LOAD MODE REGISTER command to

the mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time before initiating

any subsequent operation. Violating either of these

requirements could result in unspecified operation.

Output Drive Strength

The normal full drive strength for all outputs are

specified to be SSTL2, Class II. The x16 supports an

option for reduced drive. This option is intended for

the support of the lighter load and/or point-to-point

environments. The selection of the reduced drive

strength will alter the DQs and DQSs from SSTL2, Class

II drive strength to a reduced drive strength, which is

approximately 54 percent of the SSTL2, Class II drive

strength.

The Micron 128Mb (8 Meg x16) device supports a

programmable drive strength option.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is enabled,

200 clock cycles must occur before a READ command

can be issued.

PRELIMINARY

128Mb: x4, x8, x16

DDR SDRAM

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus

13 12 11 10 9 8 7 6 5 4 3 2 1 0 Extended Mode

01 11

Operating Mode

QFC DS DLL Register (Ex)

E0

DLL

0

Enable

1

Disable

E12 Drive Strength

0

Normal

1

Reduced

E23 QFC Function

0

Disabled

–

Reserved

E11 E10 E9 E8 E7 E6 E5 E4 E3

0 0 0 0 0 00 0 0

– – – – – –– – –

E2, E1, E0

Valid

–

Operating Mode

Normal Operation

All other states reserved

Notes: 1. E13 and E12 (BA0 and BA1) must be “1, 0” to select the

Extended Mode Register (vs. the base Mode Register).

2. The reduced drive strength option is not supported on

the x4 and x8 versions and is only available on the D3

version of the x16 device.

3. The QFC option is not supported.

Figure 3

Extended Mode Register Definition

128Mb: x4, x8, x16 DDR SDRAM

128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01

12

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2001, Micron Technology, Inc.

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