MT48LC4M8A1TG-10 データシートの表示（PDF） - Micron Technology
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MT48LC4M8A1TG-10 Datasheet PDF : 50 Pages
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OPERATION
BANK/ROW ACTIVATION
Before any READ or WRITE commands can be issued
to a bank within the SDRAM, a row in that bank must be
“opened.” This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated.
After opening a row (issuing an ACTIVE command), a
READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should be
divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a tRCD specification
of 30ns with a 90 MHz clock (11.11ns period) results in 2.7
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 < tRCD (MIN)/tCK < 3. (The same
procedure is used to convert other specification limits
from time units to clock cycles.)
A subsequent ACTIVE command to a different row in
the same bank can only be issued after the previous
active row has been “closed” (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by tRC.
A subsequent ACTIVE command to the other bank
can be issued while the first bank is being accessed,
resulting in a reduction of total row access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by tRRD.
16 MEG: x4, x8
SDRAM
Figure 3
Activating a Specific Row in a
Specific Bank
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
A0-A10
BA
ROW
ADDRESS
BANK 1
BANK 0
Figure 4
EXAMPLE: MEETING tRCD (MIN) WHEN 2 < tRCD (MIN)/tCK < 3
T0
T1
T2
T3
T4
CLK
COMMAND
ACTIVE
NOP
NOP
READ or
WRITE
tRCD
DON’T CARE
16 Meg: x4, x8 SDRAM
16MSDRAMx4x8_B.p65 – Rev. 5/98
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
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