25LC128T(2007) データシートの表示（PDF） - Microchip Technology

部品番号

コンポーネント説明

メーカー

25LC128T
(Rev.:2007)

128K SPI Bus Serial EEPROM

Microchip Technology 

25AA128/25LC128

2.7 Data Protection

The following protection has been implemented to

prevent inadvertent writes to the array:

• The write enable latch is reset on power-up

• A write enable instruction must be issued to set

the write enable latch

• After a byte write, page write or STATUS register

write, the write enable latch is reset

• CS must be set high after the proper number of

clock cycles to start an internal write cycle

• Access to the array during an internal write cycle

is ignored and programming is continued

2.8 Power-On State

The 25XX128 powers on in the following state:

• The device is in low-power Standby mode

(CS = 1)

• The write enable latch is reset

• SO is in high-impedance state

• A high-to-low-level transition on CS is required to

enter active state

TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX

WEL

(SR bit 1)

WPEN

(SR bit 7)

0

x

1

0

1

1

1

1

x = don’t care

WP

(pin 3)

x

x

0 (low)

1 (high)

Protected Blocks Unprotected Blocks STATUS Register

Protected

Protected

Protected

Protected

Protected

Writable

Writable

Writable

Protected

Writable

Protected

Writable

DS21831C-page 12

© 2007 Microchip Technology Inc.

Share Link: