28F256L18 データシートの表示（PDF） - Numonyx -> Micron
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28F256L18 Datasheet PDF : 106 Pages
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Numonyx™ StrataFlash® Wireless Memory (L18)
Table 15: AC Read Specifications, 256-Mbit, 1.7 V to 2.0 V (Sheet 2 of 2)
Num
R301
Symbol
Parameter
tAVCH/L
Address setup to CLK
Speed
–85
Min
7
Max
-
Units Notes
ns
R302
R303
tVLCH/L
tELCH/L
ADV# low setup to CLK
CE# low setup to CLK
7
-
ns
1
7
-
ns
R304
tCHQV / tCLQV CLK to output valid
-
14
ns
R305
tCHQX
Output hold from CLK
3
-
ns
1,5
R306
tCHAX
Address hold from CLK
7
-
ns
1,4,5
R307
tCHTV
CLK to WAIT valid
-
14
ns
1,5
R311
tCHVL
CLK Valid to ADV# Setup
0
-
ns
1
R312
tCHTX
WAIT Hold from CLK
3
-
ns
1,5
Notes:
1.
See Figure 8, “AC Input/Output Reference Waveform” on page 26 for timing measurements and max
allowable input slew rate.
2.
OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3.
Sampled, not 100% tested.
4.
Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5.
Applies only to subsequent synchronous reads.
6.
The specifications in Section 7.3 will only be used by customers (1) who desire a 1.35 to 2.0 VCCQ operating range
OR (2) who desire to transition their host controller from a 1.7 V to 2.0 V VCCQ voltage now to a lower range in the
future.
Figure 11: Asynchronous Single-Word Read with ADV# Low
Address [A]
R1
R2
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
R15
R17
WAIT [T]
Data [D/Q]
R7
R6
R5
RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0 Wait asserted low).
November 2007
251902-12
Datasheet
31
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