GM6535 データシートの表示（PDF） - Hynix Semiconductor

部品番号

コンポーネント説明

メーカー

GM6535

60 MHz Universal Programmable Dual PLL Frequency synthesizer

Hynix Semiconductor 

f R ,REFERENCE

(OSC in ÷ REFERENCE COUNTER)

f v ,FEEDBACK

(F in - T ÷ Tx COUNTER OR

f in -_R ÷Rx COUNTER)

TxPDout

OR

RxPD out

LD

VH

VL

VH

VL

VH

HIGH IMPEDANCE

V H = High voltage level

V L = Low voltage level

*At this point, when both fR and fv are in phase, the output is forced to near mid supply.

NOTE: The TxPDout and PxPDout generates error pulses during out-of-lock conditions.

When locked in phase and frequency, the output is high impedance and the voltage at that pin is determined

By the low-pass filter capacitor

Figure 7. Phase Detector/Lock Detector Output Waveforms

GM6535

MCU PROGRAMMING SCHEME

The MCU programming scheme is defined in

two formats controlled by the ENB input. If the

enable signal is high during the serial data transfer,

control register/reference frequency programming is

selected. If the ENB is low, programming of the

transmit and receive counters is selected. During

programming of the transmit and receive counters,

both AD in and D in pins can input the data to the

transmit and receive counters. Both counters data is

clocked into the PLL internal shift register at the

leading edge of the CLK signal. It is not necessary

to reprogram the reference frequency

counter/control register when using the enable

signal to program the transmit/receive channels.

In programming the control register/reference

frequency scheme, the most significant bit (MSB) of

the programming word identifies whether the input

data is the control word. If the MSB is 1, the input

data is the control word (Figure 8). Also see figure

NO TAG and Table 1 for control register and bit

function. If the MSB is 0, the input data is the

reference frequency (Figure 9).

The reference frequency data word is 32-bit word

containing the 12-bit reference frequency data, the

14-bit auxiliary reference frequency counter

information, the reference frequency selection plus,

the auxiliary reference frequency counter enable

bit(Figure 9).

If the AUX REF ENB bit is high, the 14-bit

auxiliary reference frequency counter provides an

additional phase reference frequency output for the

loops. If AUX REF ENB bit is low, the auxiliary

reference frequency counter is forced into power-

down modes for current saving. (other power down

modes are also provided through the control register

per Table 2 and Figure 8). At the falling edge of the

ENB signal, the data is stored in the registers.

There are two interfacing schemes for the

universal channel mode: the three-pin and four-pin

interfacing schemes. The three-pin interfacing

scheme is suited for use with the MCU SPI (serial

peripheral interface) (Figure 10), while the four-pin

interfacing scheme is commonly used for general

I/O port connection (Figure 11).

For the three-pin interfacing scheme, the

auxiliary data select bit is set to 0. All 32 bits of data,

which define both the 16-bit transmit counter and

the 16-bit receive counter, latch into the PLL

internal register though the data in pins at the

leading edge of CLK. See Figure 12 and 13.

For the four-pin interfacing scheme, the auxiliary

data select bit is set to 1. In this scheme, the 16-bit

transmit counter’s data enters into the ADin pin at

the same time as the 16-bit receive. This

simultaneous entry of the transmit and receive

counters causes the programming period of the four-

pin scheme to be half that of the three-pin scheme

(see Figures 14 and 15).

While programming Tx/Rx Channel Counter,

the ENB pin must be pulsed to provide falling edge

to latch the shifted data after the rising edge of the

last clock. Maximum data transfer rate is 500 kbps.

7

Share Link: