56F8135(2007) データシートの表示（PDF） - Freescale Semiconductor

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56F8135
(Rev.:2007)

16-bit Digital Signal Controller

Freescale Semiconductor 

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8335 and 56F8135 are organized into functional groups, as detailed

in Table 2-2 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals

present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8335

56F8135

Power (VDD or VDDA)

Power Option Control

Ground (VSS or VSSA)

Supply Capacitors1 & VPP

PLL and Clock

Bus Control

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

9

9

1

1

6

6

6

6

4

4

6

6

4

4

26

13

Serial Peripheral Interface (SPI) Port 0

Serial Peripheral Interface (SPI) Port 1

Quadrature Decoder Port 02

Quadrature Decoder Port 13

Serial Communications Interface (SCI) Ports

CAN Ports

Analog-to-Digital Converter (ADC) Ports

4

4

—

4

4

4

4

—

4

4

2

—

21

21

Timer Module Ports

6

4

JTAG/Enhanced On-Chip Emulation (EOnCE)

5

5

Temperature Sense

1

—

Dedicated GPIO (Address Bus = 11; Data Bus = 44)

28

28

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

2. Alternately, can function as Quad Timer pins or GPIO

3. Pins in this section can function as Quad Timer, SPI 1, or GPIO

4. EMI not functional in these packages; use as GPIO pins.

Note: See Table 1-1 for 56F8135 functional differences.

56F8335 Technical Data, Rev. 5

14

Freescale Semiconductor

Preliminary

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