73K324BL-IH/F データシートの表示（PDF） - Teridian Semiconductor Corporation

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73K324BL-IH/F

CCITT V.22bis,V.23,V.22,V.21,Bell 212A Single-Chip Modem w/ Integrated Hybrid

Teridian Semiconductor Corporation 

73K324BL

CCITT V.22bis,V.23,V.22,V.21, Bell 212A

Single-Chip Modem w/ Integrated Hybrid

DATA SHEET

CONTROL REGISTER 2

D7

D6

D5

D4

D3

D2

D1

D0

CR2 0

100

BIT

SPEC

REG

ACCESS

NAME

CALL

INIT

TRANSMIT

S1

16 WAY

CONDITION DESCRIPTION

RESET

DSP

TRAIN EQUALIZER

INHIBIT ENABLE

D0

Equalizer

0

The adaptive equalizer is in its initialized state.

Enable

1

The adaptive equalizer is enabled. This bit is used in

handshakes to control when the equalizer should

calculate its coefficients.

D1

Train Inhibit

0

The adaptive equalizer is active.

1

The adaptive equalizer coefficients are frozen.

D2

RESET DSP

0

The DSP is inactive and all variables are initialized.

1

The DSP is running based on the mode set by other

control bits.

D3

16 Way

0

The receiver and transmitter are using the same decision

plane (based on the modulator control mode).

1

The receiver, independent of the transmitter, is forced

into a 16 point decision plane. Used for QAM

handshaking.

D4

Transmit S1

0

The transmitter when placed in alternating mark/space

mode transmits 0101...... scrambled or not dependent on

the bypass scrambler bit.

1

When this bit is 1 and only when the transmitter is placed

in alternating mark/space mode by CR1 bits D7, D6, and

in DPSK or QAM, an unscrambled repetitive double di-bit

pattern of 00 and 11 at 1200 bps (S1) is sent

D5

Call Init

0

The DSP is set-up to do demodulation and pattern

detection based on the various mode bits. Both answer

tones are detected in demodulation mode concurrently;

TR-D0 is ignored.

1

The DSP decodes unscrambled mark, answer tone and

call progress tones.

D6

Special

0

Normal CR3 access.

Register

Access

1

Setting this bit and addressing CR3 allows access to the

special register (see the special register for details).

D7

Not used at this time

0

Only write zero to this bit.

Page: 17 of 34

© 2005, 2008 TERIDIAN Semiconductor Corporation

Rev 6.1

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