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73S8009CN データシートの表示(PDF) - Teridian Semiconductor Corporation

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73S8009CN
TERIDIAN
Teridian Semiconductor Corporation TERIDIAN
73S8009CN Datasheet PDF : 30 Pages
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DS_8009CN_026
73S8009CN Data Sheet
VDD_monitor_to_uC
VDD See NOTE 5
0.1F
C1
0.1F
C2
VPC See NOTE 1
See NOTE 4
10µH
0.1F
C3
10µF
C4
ON/OFF_Control_from_uC
USB D- to/from_uC
USB D+ to/from_uC
OFF_interrupt_to_uC
I/OUC_to/from_uC
AUX1UC_to/from_uC
AUX2UC_to/from_uC
CMDVCC%_from_uC
CMDVCC#_from_uC
RSTIN_from_uC
CLKIN_from_uC
RDY_status_to_uC
47K
47K
10K
0
See NOTE 7
1
2
3
4
I/OUC
AUX1UC
AUX2UC
CMDVCC%
5 CMDVCC#
6
7
8
RSTIN
CLKIN
RDY
73S80009CN
SC/USB_from_uC
NOTES:
1) VPC = 2.7V to 6.5V DC
47K
See NOTE 6
2) Resistor footprint is included in case some filtering is needed on CLK
3) Capacitors C5 and C6 are provisional and their footprints should be added for added noise rejection
if necessary.
4) Inductor must be rated for 400 mA maximum peak current.
5) VDD - 3.3V, +/- 0.3V, 40mA max. Schematic assumes VDD is monitored by the host controller.
Requires min two 0.1µF caps to gnd)
6) Resistors are necessary to provide isolation between powered host and "OFF" 73S8009CN. Signals
should be driven low in this condition.
7) The RDY signal is optional. A short delay before releasing RSTIN should suffice for the RDY
signal function.
ON/OFF 24
DM
I/O
AUX1
AUX2
23
22
21
20
VCC
RST
GND
19
18
17
32 QFN
See
NOTE 2
0
4.7µF
C2
VDD
R2
20K
Card detection
switch is
normally closed
27pF
C5
See
NOTE 3
27pF
C6
See
NOTE 3
0.47µF, Low ESR (<100mohms)
should be placed near the
C7
SC connecter contact
CLK track should be routed
far from RST, I/O, C4 and C8
Smart Card Connector
Figure 4: Typical 73S8009CN Application Schematic without a Main System Switch
Rev. 1.4
15

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