73S8014R データシートの表示（PDF） - Teridian Semiconductor Corporation

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73S8014R

Smart Card Interface

Teridian Semiconductor Corporation 

DS_8014R_012

73S8014R Data Sheet

CMDVCC

VCC

I/O

CLK

RSTIN

RST

t0

t1

t2

t1 = 0.510 ms (timing by 1.5MHz internal oscillator, I/O goes to reception state)

t2 = RSTIN goes low and CLK becomes active

t3 = > 0.5μs, CLK active, RST to become the copy of RSTIN

Figure 5: Activation Sequence – RSTIN High When CMDVCC Goes Low

3.7 Deactivation Sequence

Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of

hardware faults. Hardware faults are over-current, VDD fault, VCC fault, and card extraction during the session.

The following steps show the deactivation sequence and the timing of the card control signals when the system

controller sets the CMDVCC high or OFF goes low due to a fault or card removal:

- RST goes low at the end of t1.

- CLK is set low at the end of t2.

- I/O goes low at the end of t3. Out of reception mode.

- VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.

CMDVCC

OFF

-- OR --

RST

CLK

I/O

VCC

t1

t2

t3

t4

t5

t1 = > 0.5μs, timing by 1.5MHz internal Oscillator

t2 = > 7.5μs

t3 = > 0.5μs

t4 = > 0.5μs

t5 = depends on VCC filter capacitor.

Figure 6: Deactivation Sequence

Rev. 1.0

19

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