GM72V66841CT-7J データシートの表示（PDF） - LG
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GM72V66841CT-7J Datasheet PDF : 57 Pages
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Function Truth Table (Continued)
GM72V66841CT/CLT
Current
state
CS RAS CAS WE Address
Refresh
H X X XX
(auto-refresh)
L H H HX
Command
DESL
NOP
Operation
Enter IDLE after tRC
Enter IDLE after tRC
L H H LX
BST
Enter IDLE after tRC
L H L H BA, CA, A10 READ/READ A ILLEGAL
L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL
L L H H BA, RA
ACTV
ILLEGAL
L L H L BA, A10 PRE, PALL ILLEGAL
L L L HX
REF, SELF
ILLEGAL
L L L L MODE
MRS
ILLEGAL
* Notes : 1. H: VIH, L: VIL, X: VIH or VIL.
The other combinations are inhibit.
2. An interval of tRWL is required between the final valid data input and the Precharge command.
3. If tRRD is not satisfied, this operation is illegal.
4. BA:Bank Address, RA:Row Address, CA:Column Address
From [Precharge]
To [DESL], [NOP] or [BST]: When these
commands are executed, the synchronous
DRAM enters the IDLE state after tRP has
elapsed from the completion of Precharge
From [IDLE]
To [DESL], [NOP], [BST], [PRE] or
[PALL]: These commands result in no
operation.
To [ACTV]: The bank specified by the
address pins and the ROW address is
activated.
To [REF], [SELF]: The synchronous
DRAM enters refresh mode (auto-refresh or
self-refresh).
To [MRS]: The synchronous DRAM enters
the mode register set cycle.
12
From [ROW ACTIVE]
To [DESL], [NOP] or [BST]: These
commands result in no operation.
To [READ], [READ A]: A read operation
starts. (However, an interval of tRCD is
required.)
To [WRIT], [WRIT A]: A write operation
starts. (However, an interval of tRCD is
required.)
To [ACTV]: This command makes the
other bank active. (However, an interval of
tRRD is required.) Attempting to make the
currently active bank active results in an
illegal command.
To [PRE], [PALL]: These commands set
the synchronous DRAM to Precharge
mode. (However, an interval of tRAS is
required.)
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