GM72V66841CLT-8 データシートの表示（PDF） - LG

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GM72V66841CLT-8

2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM

LG 

LG Semicon

GM72V66841CT/CLT

Operation of

GM72V661641CT/CLT, GM72V66841CT/CLT,

GM72V66441CT/CLT Series

Read / Write Operation

Bank active: Before executing a read or write

operation, the corresponding bank and the row

address must be activated by the bank active

(ACTV) command. Bank 0, bank 1, bank 2 or

bank 3 is activated according to the status of the

A12/A13 pin, and the row address (AX0 to

AX11) is activated by the A0 to A11 pins at the

bank active command cycle. An interval of tRCD

is required between the bank active command

input and the following read/write command

input.

Read operation: A read operation starts when a

read command is input. Output buffer becomes

Low-Z in the (CAS Latency - 1) cycle after read

command set. GM72V66841CT/CLT can perform a

burst read operation.

The burst length can be set to 1, 2, 4, 8 or full

page(512;GM72V66841CT/CLT). The start address

for a burst read is specified by the column

address (AY0 to AY8; GM72V66841CT/CLT) and

the bank select address (A12/A13) at the read

command set cycle. In a read operation, data

output starts after the number of cycles specified

by the CAS Latency. The CAS Latency can be

set to 2 or 3.

When the burst length is 1, 2, 4, or 8, the Dout

buffer automatically becomes High-Z at the next

cycle after the successive burst-length data has

been output.

When the burst length is full-page

(512;GM72V66841CT/CLT) data is repeatedly

output until the burst stop command is input.

The CAS latency and burst length must be

specified at the mode register.

CAS Latency

CLK

Command

Address

tRCD

ACTV

READ

Row

Column

Dout

CL = 2

CL = 3

out 0 out 1 out 2 out 3

out 0 out 1 out 2 out 3

CL : CAS Latency

Burst Length = 4

17

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