DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

78Q2120C データシートの表示(PDF) - Teridian Semiconductor Corporation

部品番号
コンポーネント説明
メーカー
78Q2120C
TERIDIAN
Teridian Semiconductor Corporation TERIDIAN
78Q2120C Datasheet PDF : 35 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
78Q2120C
10/100BASE-TX
Transceiver
MR0: Control Register (continued)
BIT
0.8
0.7
0.6:0
SYMBOL
DUPLEX
COLT
RSVD
TYPE
R/W
R/W
R
DEFAULT
(1)
0
0
DESCRIPTION
Duplex Mode: This bit determines whether the device supports full-
duplex or half-duplex. A ‘1’ indicates full-duplex operation and a ‘0’
indicates half-duplex. This bit will default to ‘0’ upon reset and will
be writeable if the TECH[2:0] pins are all logic zero and auto-
negotiation is not enabled. If auto-negotiation is not enabled and
the TECH[2:0] pins are set to indicate that only full-duplex is
supported, this bit will be forced to ‘1’ and will not be writeable. If
auto-negotiation is not enabled and the TECH[2:0] pins are set to
indicate that only half-duplex is supported, this bit will be forced to
‘0’ and will not be writeable. When auto-negotiation is enabled, this
bit will not be writeable and will have no effect on the device. If the
TECH[2:0] pins are brought to zero from another value, this bit will
retain its original value until it is overwritten.
Collision Test: When this bit is set to ‘1’, the device will assert the
COL signal in response to the assertion of the TX_EN signal.
Collision test is disabled if the PCSBP pin is high. Collision test can
be activated regardless of the duplex mode of operation.
Reserved
MR1: Status Register
Bits 1.15 through 1.11 reflect the ability of the 78Q2120C as configured by the TECH[2:0] pins. They do not
reflect any ability changes made via the MII Management interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and
0.8 (DUPLEX).
BIT SYMBOL TYPE DEFAULT DESCRIPTION
1.15
100T4
R
0
100BASE-T4 Ability: Reads ‘0’ to indicate the 78Q2120C does not
support 100Base-T4 mode.
1.14 100X_F R
(1)
100BASE-TX Full Duplex Ability:
0 : Not able
1 : Able
1.13 100X_H R
(1)
100BASE-TX Half Duplex Ability:
0 : Not able
1 : Able
1.12 10T_F
R
(1)
10BASE-T Full Duplex Ability:
0 : Not able
1 : Able
1.11 10T_H
R
(1)
10BASE-T Half Duplex Ability:
0 : Not able
1 : Able
1.10 100T2_F R
0
100BASE-T2 Full Duplex Ability: Reads ‘0’ to indicate the
78Q2120C does not support 100Base-T2 full duplex mode.
Page: 12 of 35
© 2009 Teridian Semiconductor Corporation
Rev 1.3

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]