M5LV-256/74-5YI データシートの表示（PDF） - Lattice Semiconductor

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M5LV-256/74-5YI

MACH 5 CPLD Family Fifth Generation MACH Architecture

Lattice Semiconductor 

100-PIN TQFP CONNECTION DIAGRAM – 68 I/O

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100-Pin TQFP (68 I/O)

M5-128

M5LV-128

M5-192

M5-256

M5LV-256*

M5-128

M5LV-128

M5-192

M5-256

M5LV-256*

TDI

1

0A14 0A12 0A12

I/O0

2

0B13 0B13 0B13

I/O1

3

0B12 0B12 0B12

I/O2

4

0B11 0B11 0B11

I/O3

5

0B8 0B8 0B8

I/O4

6

0B7 0B7 0B7

I/O5

7

0B4 0B4 0B4

I/O6

8

0B3 0B3 0B3

I/O7

9

0B2 0B2 0B2

I/O8

10

I0/CLK0

11

VCC

12

GND

13

GND

14

I1/CLK1

15

1B2 1B2 1B2

I/O9

16

1B3 1B3 1B3 I/O10

17

1B4 1B4 1B4 I/O11

18

1B7 1B7 1B7 I/O12

19

1B8 1B8 1B8 I/O13

20

1B11 1B11 1B11 I/O14

21

1B12 1B12 1B12 I/O15

22

1B13 1B13 1B13 I/O16

23

1A14 1A12 1A12 I/O17

24

TCK

25

75

GND

74

TDO

73

I/O51 3A12 2A12 0D14

72

I/O50 3B13 2B13 0C13

71

I/O49 3B12 2B12 0C12

70

I/O48 3B11 2B11 0C11

69

I/O47 3B8 2B8 0C8

68

I/O46 3B7 2B7 0C7

67

I/O45 3B4 2B4 0C4

66

I/O44 3B3 2B3 0C3

65

I/O43 3B2 2B2 0C2

64

I3/CLK3

63

GND

62

VCC

61

I2/CLK2

60

I/O42 2B2 2C2 1C2

59

I/O41 2B3 2C3 1C3

58

I/O40 2B4 2C4 1C4

57

I/O39 2B7 2C7 1C7

56

I/O38 2B8 2C8 1C8

55

I/O37 2B11 2C11 1C11

54

I/O36 2B12 2C12 1C12

53

I/O35 2B13 2C13 1C13

52

I/O34 2A12 2D12 1D14

51

TMS

M5-256

M5LV-256*

M5-192

M5-128

M5LV-128

*Package obsolete, contact factory.

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O = Input/Output

NC = No Connect

VCC = Supply Voltage

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

M5-256

M5LV-256*

M5-192

M5-128

M5LV-128

20446G-017

3 D 15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

29

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