82541 データシートの表示（PDF） - Intel
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82541 Datasheet PDF : 46 Pages
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Networking Silicon — 82541(PI/GI/EI)
AC Test Loads for General Output Pins
Symbol
CL
CL
CL
CL
TDO
PME#, SDP[3:0]
EEDI, EESK
LED[3:0]
Signal Name
Figure 3. AC Test Loads for General Output Pins
Value
10
16
18
20
Units
pF
pF
pF
pF
CL
4.5
Timing Specifications
Table 17. PCI Bus Interface Clock Parameters
Symbol
Parametera
PCI 66 MHz
Min
Max
PCI 33 MHz
Min
Max
Units
TCYC
TH
TL
CLK cycle time
CLK high time
CLK low time
CLK slew rate
RST# slew rateb
15
30
30
6
11
6
11
1.5
4
1
50
50
ns
ns
ns
4
V/ns
mV/ns
a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the
minimum peak-to-peak portion of the clock waveform as shown.
b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system
noise cannot render a monotonic signal to appear bouncing in the switching range.
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