82541ER データシートの表示（PDF） - Intel
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82541ER Datasheet PDF : 46 Pages
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82541(PI/GI/EI) — Networking Silicon
Figure 4. AC Test Loads for General Output Pins
3.3 V Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
Th
0.6 Vcc
Tcyc
0.2 Vcc
Tl
0.4 Vcc p-to-p
(minimum)
Table 18. PCI Bus Interface Timing Parameters
Symbol
Parameter
PCI 66MHz
Min
Max
TVAL
CLK to signal valid delay: bussed
signals
2
6
TVAL(ptp)
CLK to signal valid delay: point-
to-point signals
2
6
TON
Float to active delay
2
TOFF
Active to float delay
14
TSU
Input setup time to CLK: bussed
signals
3
TSU(ptp)
Input setup time to CLK: point-to-
point signals
5
TH
Input hold time from CLK
0
PCI 33 MHz
Min
Max
2
11
2
12
2
28
7
10, 12
0
Units
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Output timing measurements are as shown.
2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than
bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.
3. Input timing measurements are as shown.
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