82574L データシートの表示（PDF） - Intel

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82574L

82574 GbE Controller

Intel 

Introduction—82574 GbE Controller

1.5

82574 Architecture Block Diagram

Figure 1 shows a high-level architecture block diagram for the 82574.

RMII

SMBus

PCIe

RMII I/F

NC-SI

SMBus

I/F

PCIe I/F

Rx/Tx DMA

Rx/Tx FIFO

Transmit

Switch

Filter

MAC

Rx/Tx FIFO

PHY

Link

Figure 1.

1.6

1.7

82574 Architecture Block Diagram

System Interface

The 82574 provides one PCIe lane operating at 2.5 GHz with sufficient bandwidth to

support 1000 Mb/s transfer rate. 40 KB of on-chip buffering mitigates instantaneous

receive bandwidth demands and eliminates transmit under–runs by buffering the entire

outgoing packet prior to transmission.

Features Summary

This section describes the 82574’s features that were present in previous Intel client

GbE controllers and those features that are new to the 82574.

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