A29040B Series
Timing Waveforms for Data Polling (During Embedded Algorithms)
Addresses
CE
tCH
OE
WE
I/O7
tRC
VA
tACC
tCE
tOE
tOEH
tDF
tOH
Complement
VA
Complement True
VA
Valid Data
High-Z
I/O0 - I/O6
Status Data
Status Data True
Valid Data
High-Z
Note : VA = Valid Address. Illustation shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Timing Waveforms for Toggle Bit (During Embedded Algorithms)
Addresses
CE
tCH
OE
WE
I/O6 , I/O2
tRC
VA
tACC
tCE
tOE
tOEH
tDF
tOH
Valid Status
(first read)
VA
Valid Status
(second read)
VA
VA
Valid Status
(stop togging)
Valid Status
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
PRELIMINARY (December, 2004, Version 0.2)
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AMIC Technology, Corp.