ACD2203S8GP1 データシートの表示（PDF） - ANADIGICS

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ACD2203S8GP1

CATV/TV/Video Downconverter with Dual Synthesizer

ANADIGICS 

ACD2203

Table 13: Main Divider A Counter Bits

VALUE OF A A A A A A A A

COUNTER 7 6 5 4 3 2 1

0

0000000

1

000000 1

-

-------

127

Notes:

B > A, A < P

1111111

Table 14: Phase Detector Polarity Bit

SS

D

2

1

1

00

PLL2 Phase Detector Polarity

10

PLL1 Phase Detector Polarity

Bit C1 in each main divider register sets the

prescalar mode. Table 16 indicates the appropriate

settings. (Currently, there is only one prescalar

mode available for use.)

Table 16: Prescalar Mode

C

1

PRESCALAR MODE

0

64/65

1

(reserved for future use)

Bit C2 in the main divider registers, bits D2 through

D5 in the reference divider registers, and bits X1

and X2 in all registers are reserved for future use,

and have no current function. They can be set either

high or low without affecting synthesizer

performance.

Programmable Modes

Each register contains bits set aside for programming

different modes of operation in the synthesizers. Bit

D1 in each reference divider register controls the phase

detector polarity. Table 14 shows how this bit controls

the polarity, and the correct setting is determined by

using Table 15 and Figure 22.

Table 15: Phase Detector Polarity Selection

D

VCO

1 POLARITY CHARACTERISTICS

0

Negative

curve (2)

1

Positive

curve (1)

(1)

VCO OUTPUT

FREQUENCY

(2)

VCO INPUT VOLTAGE

Figure 22: VCO Characteristics

14

PRELIMINARY DATA SHEET - Rev 1.3

12/2003

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