ACS715LLCTR-30A-T データシートの表示（PDF） - Allegro MicroSystems
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ACS715LLCTR-30A-T
Allegro MicroSystems
ACS715LLCTR-30A-T Datasheet PDF : 13 Pages
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ACS715
Automotive Grade, Fully Integrated, Hall Effect-Based Linear Current Sensor
with 2.1 kVRMS Voltage Isolation and a Low-Resistance Current Conductor
Chopper Stabilization Technique
Chopper Stabilization is an innovative circuit technique that is
used to minimize the offset voltage of a Hall element and an asso-
ciated on-chip amplifier. Allegro patented a Chopper Stabiliza-
tion technique that nearly eliminates Hall IC output drift induced
by temperature or package stress effects. This offset reduction
technique is based on a signal modulation-demodulation process.
Modulation is used to separate the undesired dc offset signal from
the magnetically induced signal in the frequency domain. Then,
using a low-pass filter, the modulated dc offset is suppressed
while the magnetically induced signal passes through the filter.
As a result of this chopper stabilization approach, the output
voltage from the Hall IC is desensitized to the effects of tempera-
ture and mechanical stress. This technique produces devices that
have an extremely stable Electrical Offset Voltage, are immune to
thermal stress, and have precise recoverability after temperature
cycling.
This technique is made possible through the use of a BiCMOS
process that allows the use of low-offset and low-noise amplifiers
in combination with high-density logic integration and sample
and hold circuits.
Regulator
Hall Element
Clock/Logic
Amp
Low-Pass
Filter
Concept of Chopper Stabilization Technique
Typical Applications
+5 V
+5 V
CBYP
0.1 μF
R1
33 kΩ
1 IP+
8
VCC
2 IP+
7
VIOUT
R2
100 kΩ
VOUT
RPU
100 kΩ
4
–
5
1
Fault
IP
ACS715
3 IP– FILTER 6
4 IP– GND 5
CF
3 + 2 U1
LMV7235
D1
1N914
Application 2. 10 A Overcurrent Fault Latch. Fault threshold
set by R1 and R2. This circuit latches an overcurrent fault
and holds it until the 5 V rail is powered down.
VS1
CBYP
0.1 μF
R1
100 kΩ
R2
100 kΩ
1 IP+
8
VCC
2 IP+
7
VIOUT
IP
ACS715
RF
1 kΩ
3 IP– FILTER 6
4 IP–
5
GND
CF
0.01 μF
1+
LM321
5
4
3–
2
R3
3.3 kΩ
VOUT
C1
1000 pF
Application 3. This configuration increases gain to 610 mV/A
(tested using the ACS712ELC-05A).
+5 V
VS2
+5 V
Application 4. Control circuit for MOSFET ORing.
1 IP+
8
VCC
2 IP+
7
VIOUT
VOUT
CBYP
0.1 μF
+
IP1
ACS715
3 IP– FILTER 6
4 IP– GND 5
VREF –
CF
U1
LMC6772
Q3
2N7002
Q1
FDS6675a
R3
10 kΩ
1 IP+
8
VCC
2 IP+
7
VIOUT
VOUT
CBYP
0.1 μF
+
IP2
ACS715
3 IP– FILTER 6
4 IP– GND 5
VREF –
CF
U2
LMC6772
Q2
FDS6675a
R4
10 kΩ
Q4
2N7002
R1
100 kΩ
LOAD
R2
100 kΩ
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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