ACS8522BT データシートの表示（PDF） - Semtech Corporation

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ACS8522BT

Synchronous Equipment Timing Source for Stratum 3/4E/4, SMC and Ethernet Systems

Semtech Corporation 

ACS8522BT eSETS

ADVANCED COMMS & SENSING

FINAL

DATASHEET

Table 4 Input Reference Source Selection and Priority Table

Input Port

Channel

Number (Bin)

Input Port

Technology

SEC1

0011

TTL/CMOS

SEC2

0100

TTL/CMOS

SEC3

1000

TTL/CMOS

SEC4

1001

TTL/CMOS

Frequencies Supported

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

Up to 100 MHz (see Note (i))

Default (SONET): 8 kHz Default (SDH): 8 kHz

Up to 100 MHz (see Note (i))

Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz

Up to 100 MHz (see Note (i))

Default (SONET): 19.44 MHz Default (SDH): 19.44 MHz

Default

Priority

2

3

4

5

Note: (i) TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot frequency being

77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz (and N x 8 kHz), 1.544 MHz (SONET)/2.048 MHz (SDH), 6.48 MHz,

19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET or SDH input rate is selected via Reg. 34 Bit 2, ip_sonsdhb).

DivN Mode

In DivN mode, the divider parameters are set manually by

configuration (Bit 7 of the cnfg_ref_source_frequency

register), but must be set so that the frequency after

division is 8 kHz. The DivN function is defined as:

DivN = “Divide by N+ 1”, i.e. it is the dividing factor used

for the division of the input frequency, and has a value of

(N+1) where N is an integer from 1 to 12499 inclusive.

Therefore, in DivN mode the input frequency can be

divided by any integer value between 2 to 12500.

Consequently, any input frequency which is a multiple of

8 kHz, between 8 kHz to 100 MHz, can be supported by

using DivN mode.

Note...Any reference input can be set to use DivN

independently of the frequencies and configurations of the

other inputs. However only one value of N is allowed, so all

inputs with DivN selected must be running at the same

frequency.

DivN Examples

(a) To lock to 2.000 MHz:

(i) Set the cnfg_ref_source_frequency register to

10XX0000 (binary) to enable DivN, and set the

frequency to 8 kHz - the frequency required after

division. (XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 2 MHz input must be

divided by 250. So, if DivN = 250 = (N + 1)

then N must be set to 249. This is done by writing

F9 hex (249 decimal) to the DivN register pair

Reg. 46/47.

(b) To lock to 10.000 MHz:

(i) The cnfg_ref_source_frequency register is set to

10XX0000 (binary) to set the DivN and the

frequency to 8 kHz, the post-division frequency.

(XX = “Leaky Bucket” ID for this input).

(ii) To achieve 8 kHz, the 10 MHz input must be

divided by 1250. So, if DivN, = 1250 = (N+1)

then N must be set to 1,249. This is done by

writing 4E1 hex (1,249 decimal) to the DivN

register pair Reg. 46/47.

Clock Quality Monitoring

Clock quality is monitored and used to modify the priority

tables. The following parameters are monitored:

1. Activity (toggling).

2. Frequency (this monitoring is only performed when

there is no irregular operation of the clock or loss of

clock condition).

Any reference source that suffers a loss-of-activity or

clock-out-of-band condition will be declared as

unavailable.

Clock quality monitoring is a continuous process which is

used to identify clock problems. There is a difference in

dynamics between the selected clock and the other

reference clocks. Anomalies occurring on non-selected

reference sources affect only that source's suitability for

selection.

Revision 1.00/April 2010© Semtech Corp.

Page 11

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