AD12401-XXXJWS データシートの表示（PDF） - Analog Devices

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AD12401-XXXJWS

12-Bit, 400 MSPS A/D Converter

Analog Devices 

The SMA edge connectors (AIN and ENC/ENC) are surface

mounted to the board to achieve minimum height of the

module. When attaching and routing the cables, one must

ensure they are stress-relieved and do not apply stress to the

SMA connector/board. The presence of stress on the cables can

degrade electrical performance and mechanical integrity of the

module. In addition to the routing precautions, the smallest

torque necessary to achieve consistent performance should be

used to secure the system cable to the AD12401’s SMA

connectors. The torque should never exceed 5-inch pounds.

Any disturbances to the AD12401 structure, including

removing the covers or mounting screws, invalidates the

calibration and results in degraded performance. See the

Outline Dimensions section for mounting stud dimensions, see

Figure 38 for PCB interface locations. Mounting stud length

typically accommodates a PCB thickness of 0.093". Consult

sales if board thickness requirements exceed this dimension.

AD12401 EVALUATION KIT

The AD12401/KIT offers an easy way to evaluate the AD12401.

The AD12401/KIT includes the AD12401 mounted on an

adapter card, the AD12401 evaluation board, the power supply

cables, a 225 MHz buffer memory FIFO board, and the Dual

Analyzer software. The user must supply a clock source, an

analog input source, a 1.5 V power supply, a 3.3 V power supply,

a 5 V power supply, and a 3.8 V power supply. The clock source

and analog input source connect directly to the AD12401. The

power supply cables (included) and a parallel port cable (not

included) connect to the evaluation board. The AD12401

works on the same evaluation board as the AD12400 and the

AD12500: GS08054.

Power Connector

Power is supplied to the board via a detachable 12-lead power

strip (three 4-pin blocks).

Table 11. Power Connector

Supply Description

VA 3.7 V Analog supply for the ADC (950 mA typ)

VC 3.3 V Digital supply for the ADC outputs (400 mA typ)

VD 1.5 V1 Digital supply for the FPGA (1.25 A max, 0.7 A typ)

VB 5.0 V Digital supply for the buffer memory board (400 mA typ)

1 The power supply cable has an approximately 100 mV drop. The VD supply

current is dependent on the analog input frequency (see Figure 17).

Analog Input

The analog input source connects directly to an SMA on the

AD12401.

H/L_GAIN

The H/L_GAIN select jumper, Pin 103, should be on for low

gain mode (AD12401-xxxKWS). The H/L_GAIN select jumper

should be removed for high gain mode, AD12401-xxxJWS.

AD12401

ENCODE

The single-ended or differential ENCODE signal connects directly

to SMA connector(s) on the AD12401. A single-ended sine wave

at 10 dBm connected to the ENCODE SMA is recommended.

A low jitter clock source (<0.5 ps) is recommended to properly

evaluate the AD12401.

DATA OUTPUTS

The AD12401xxxKWS digital outputs are available at the 80-pin

connector, P2, on the evaluation board. The AD12401/KIT

comes with a buffer memory FIFO board connected to P2,

which provides the interface to the parallel port of a PC. The

Dual Analyzer software is compatible with Windows® 95,

Windows 98, Windows 2000, and Windows NT®.

The buffer memory FIFO board can be removed, and an external

logic analyzer or other data acquisition module can be connected

to this connector, if required.

Adapter Card

The AD12401 is attached to an adapter card that interfaces to

the evaluation board through a 120-pin connector, P1, which is

on the top side of the evaluation board.

Digital Postprocessing Control

The evaluation board has a 2-pin jumper, labeled AFB, that

allows the user to enable/disable the digital postprocessing. The

digital postprocessing is active when the AFB jumper is applied.

When the jumper is removed, the FPGA is set to a passthrough

mode, which demonstrates to the user the performance of the

AD12401 without the digital postprocessing.

RESET

The AD12401’s FPGA configuration is stored in an EEPROM

and loaded into the FPGA when power is applied to the AD12401.

The RESET switch, SW1 (active low), allows the user to reload

the FPGA in case of a low voltage condition or a power supply

glitch. Depressing the RESET switch pulls the data-ready and

output bits high. The RESET switch should remain low for a

minimum of 200 ns. On the rising edge of the RESET pulse, the

AD12401 starts loading the configuration into the on-module

FPGA. The reload process requires a maximum of 600 ms to

complete. Valid signals on the data-ready pins indicate the reset

process is complete.

The AD12401 is not compatible with the HSC-ADC-EVAL-

DC/SC hardware or software.

Rev. A | Page 21 of 28

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