AD1991 データシートの表示（PDF） - Analog Devices
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AD1991 Datasheet PDF : 12 Pages
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PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
PGND1 1
OUTA 2
OUTA 3
OUTA 4
PVDD1 5
PVDD1 6
PVDD1 7
OUTB 8
OUTB 9
OUTB 10
PGND1 11
PGND1 12
PGND1 13
PIN 1
IDENTIFIER
AD1991
TOP VIEW
(Not to Scale)
39 PGND2
38 OUTC
37 OUTC
36 OUTC
35 PVDD2
34 PVDD2
33 PVDD2
32 OUTD
31 OUTD
30 OUTD
29 PGND2
28 PGND2
27 PGND2
14 15 16 17 18 19 20 21 22 23 24 25 26
AD1991
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic In/Out Description
1
2, 3, 4
5, 6, 7
8, 9, 10
11, 12, 13
14
15
16
17
PGND1
OUTA
O
PVDD1
OUTB
O
PGND1
ERR3
I/O
ERR2
I/O
ERR1
I/O
ERR0
I/O
18
INA
I
19
INB
I
20
DVDD
21
DGND
22
MUTE
I
23
INC
I
24
IND
I
25
RST/PDN I
26
CLK
I
27, 28, 29 PGND2
30, 31, 32 OUTD
O
33, 34, 35
PVDD2
36, 37, 38 OUTC
O
39, 40, 41, 42 PGND2
43, 45, 48, 49 AGND
44
MODE0
46
AVDD
47
MODE1 I
50, 51, 52 PGND1
Negative power supply for high power Transistors A2 and B2.
Output of transistor pair A1 and A2.
Positive power supply for high power Transistors A1 and B1.
Output of transistor pair B1 and B2.
Negative power supply for high power Transistors A2 and B2.
Edge speed setting MSB during RESET/active low thermal shutdown error output during
normal operation.
Edge speed setting Bit 1 during RESET/active low thermal warning error output during
normal operation.
Nonoverlap time setting MSB during RESET/active thermal low shutdown error output
during normal operation.
Nonoverlap time setting Bit 1 during RESET/active low data-loss error output or low-side
transistor disable input during normal operation.
Control pin for Transistors A1 and A2 always; also control pin for B1 and B2 in 2-channel mode.
Edge speed setting LSB during RESET/during normal operation, control pin for Transistors
B1 and B2 in 4-channel mode; no function in 2-channel mode.
Positive power supply for low power digital circuitry.
Negative power supply for low power digital circuitry.
Active low clickless mute input.
Control pin for Transistors C1 and C2 always; also control pin for D1 and D2 in 2-channel mode.
Nonoverlap time setting LSB during RESET/during normal operation, control pin for Transis-
tors D1 and D2 in 4-channel mode; no function in 2-channel mode.
Active low RESET/power-down input.
External clock input in external clock mode.
Negative power supply for high power Transistors C2 and D2.
Output of transistor pair D1 and D2.
Positive power supply for high power Transistors C1 and D1.
Output of transistor pair C1 and C2.
Negative power supply for high power Transistors C2 and D2.
Negative power supply for low power analog circuitry.
Clock source select (referenced to AGND); normally connected to AGND.
Positive power supply for low power analog circuitry.
Channel mode select (referenced to AGND).
Negative power supply for high power Transistors A2 and B2.
REV. 0
–5–
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