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AD5100(Rev0) データシートの表示(PDF) - Analog Devices

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AD5100 Datasheet PDF : 36 Pages
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AD5100
Parameter
MR (MANUAL RESET) INPUT
MR Input Voltage Low
MR Input Voltage High
Input Current
MR Pulse Width
MR Deglitching
MR-to-RESET Delay
MR Pull-Up Resistance (Internal to V3MON)
RESET Hold Time Tolerance
(see Figure 12 and Table 8)
SERIAL INTERFACES
Input Logic High (SCL, SDA)6
Input Logic Low (SCL, SDA)
Output Logic High (SDA)
Output Logic Low (SDA)
Input Current
Input Capacitance
POWER SUPPLY
Supply Voltage Range
Sleep Mode Supply Current
Active Mode Supply Current
Device Power-On Threshold
Device Power-Up V2MON, Minimum Pulse Width
Device Power-Down Delay
OTP Supply Voltage7
OTP Supply Current8
OTP Settling Time9
Symbol
VIL_MR
VIH_MR
tMR
tMR_GLITCH
tMR_DELAY
ΔtRS_HOLD
VIH
VIL
VOH
VOL
CI
V1MON
ISLEEP_V1MON
IPOWER_V1MON
V2MON, IH
V2MON, IL
tV2MON_PW
TVREG_OFF_DELAY
VOTP
IVOTP
tS_OTP
Conditions
TA = 25°C; does not apply to
Code 0x6 and Code 0x7
TA = −40°C to +125°C; does
not apply to Code 0x06 and
Code 0x7
External RPULL-UP = 2.2 kΩ
External RPULL-UP = 2.2 kΩ
VRAIL = 2 V to 5.5 V
IOL = 3 mA
VIN = 0 V to 5.5 V
V2MON = 0 V
V2MON = 12 V
V2MON edge triggered mode
selected
V2MON < 0.4 V (normal mode)
I2C-initiated power-down
For OTP only
For OTP only
Min
Typ1 Max
Unit
0.7 × V3MON
1
100
1
50
60
−10
−17
0.3 × V3MON V
V
1
μA
μs
ns
μs
75
+10
%
+17
%
2.0
5.5
V
0
0.8
V
0.7 × VRAIL
V
0
0.4
V
1
μA
5
pF
6.0
30
V
5
μA
2
mA
2
mA
2.2
V
0.4
V
4
ms
2
sec
10
μs
5.5
V
84
mA
12
ms
1 Represent typical values at 25°C, V1MON = 12 V, and V2MON = 12 V.
2 Initial V2MON turn-on minimum remains as 2.2 V but the 3 V to 30 V specifications apply afterward.
3 Does not apply if V2MON is a digital signal.
4 V4MON threshold limits (see Table 6) are designed to primarily allow V4MON to monitor low voltage inputs. The V4MON input pin is capable of withstanding voltages up to
30 V. One application where this 30 V capability is useful is electronic media-oriented systems transport (eMOST) diagnostic circuits.
5 The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a microprocessor bidirectional reset pin.
6 It is typical for the SCL and SDA to have resistors pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are
driven directly from a low voltage logic controller without pull-up resistors.
7 VOTP can be furnished by an external 5.5 V power supply, rather than an on-board power supply, when performing factory programming. A 10 μF tantalum capacitor is
required on VOTP during operation regardless of whether the OTP fuses are programmed.
8 The OTP supply source must be capable of supplying a minimum of 100 mA because some AD5100 parts require a current slightly greater than the typical value
of 84 mA.
9 The OTP settling time occurs only once if the OTP function is used.
Rev. 0 | Page 6 of 36

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