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AD5100YRQZ データシートの表示(PDF) - Analog Devices

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AD5100YRQZ Datasheet PDF : 32 Pages
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Preliminary Technical Data
AD5100
Parameter
Symbol
Conditions
Min
Typ1 Max
Unit
Sleep Mode Supply Current
ISLEEP_V1MON
V2MON = 0 V
10
μA
Active Mode Supply Current
IPOWER_V1MON
V2MON = 12 V
3
mA
V2MON Edge Triggered Mode
Selected
3
mA
Device Power On Threshold
V2MON,IH
2.2
V
V2MON,IL
0.4
V
Device Power Up V2MON Minimum
Pulse Width (Figure 14)
tV2MON_PW
4
ms
Device Power Down Delay
V2MON < 0.4V (Normal Mode)
2
s
I2C Initiated Power Down
10
μs
OTP Supply Voltage6
VOTP
For OTP only
6
6.5
V
OTP Supply Current
OTP Settling Time7
IVOTP
tS_OTP
For OTP only
200
mA
12
ms
TIMING CHARACTERISTICS 8
Parameter Adjustment Time
tS1
1
μs
I2C Interface Timing
Characteristics
SCL Clock Frequency
fSCL
400
KHz
tBUF Bus Free Time between Start
t1
and Stop
1.3
μs
tHD;STA Hold Time after (Repeated)
t2
START condition. After this period,
the first clock is generated
0.6
μs
tLOW Low Period of SCL Clock
t3
1.3
μs
tHIGH High Period of SCL Clock
t4
0.6
50
μs
tSU;STA Setup Time for Start
t5
Condition
0.6
μs
tHD;DAT Data Hold Time
t6
0.9
μs
tSU;DAT Data Setup Time
t7
0.1
μs
tF Fall Time of Both SDA and SCL
t8
Signals
0.3
μs
tR Rise Time of Both SDA and SCL t9
Signals
0.3
μs
tSU;STO Setup Time for Stop
t10
Condition
0.6
μs
Notes:
1. Represent typical values at 25°C, V1MON = 12 V, and V2MON = 12 V.
2. Does not apply if V2MON is a digital signal.
3. The RESET short-circuit current is the maximum pullup current when RESET is driven low by a μP bidirectional reset pin.
4. It is typical for the SCL and SDA have resistors to be pulled up to V3MON. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage
logic controller without pull-up resistors.
5. Initial V2MON ON minimum remains as 2.2V but the -0.3V to 30V specifications apply afterwards.
6. VOTP can be furnished by Factory 6V power supply, rather than on-board power supply, when performing factory programming. A 10uF tantalum capacitor is required on VOTP during operation regardless
of whether the OTP fuses are programmed.
7. The OTP settling time occurs only once if OTP function is used.
8. Guaranteed by design and not subject to production test.
t8
t6
t9
t2
SCL
t2
t3
t4
t8
t9
SDA
t1
P
S
Figure 2. Digital Interface Timing Diagram
t7
t5
S
t10
P
Rev. PrJ | Page 5 of 32

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