AD5533ABC-1_ データシートの表示（PDF） - Analog Devices
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AD5533ABC-1_ Datasheet PDF : 16 Pages
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09/19/02 2:30 PM_GS
AD5532B
The power supply lines of the AD5532B should use as large a trace
as possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the DIN and
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane,
but separating the lines will help).
Note that it is essential to minimize noise on VIN and REFIN
lines. Particularly for optimum ISHA performance, the VIN line
must be kept noise-free. Depending on the noise performance of
the board, a noise filtering capacitor may be required on the VIN
line. If this capacitor is necessary, then for optimum throughput
it may be necessary to buffer the source that is driving VIN.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on the
solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
1.70
MAX
OUTLINE DIMENSIONS
74-Lead Chip Scale Ball Grid Array [CSPBGA]
(BC-74)
Dimensions shown in millimeters
12.00 BSC
SQ
A1
TOP VIEW
1.00
BSC
A1 CORNER
INDEX AREA
11 10 9 8 7 6 5 4 3 2 1
BOT TOM
VIEW
A
B
C
D
E
F 10.00 BSC
G SQ
H
J
K
L
DETAIL A
1.00 BSC
DETAIL A
0.30 MIN
0.20 MAX
COPLANARITY
0.70
0.60
SEATING
0.50
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-192ABD-1
Revision History
Location
Page
9/02—Data Sheet changed from REV. 0 to REV. A.
Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
Changes to SERIAL INTERFACE table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Replaced Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Updated BC-74 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
–16–
REV. A
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