AD5541BR データシートの表示（PDF） - Analog Devices
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AD5541BR Datasheet PDF : 20 Pages
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AD5541/AD5542
Data Sheet
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
( ) VOUT-UNI
=
D
2 16
×
VREF
+ VGE
+ VZSE + INL
where:
VOUT−UNI is unipolar mode worst-case output.
D is code loaded to DAC.
VREF is reference voltage applied to the part.
VGE is gain error in volts.
VZSE is zero scale error in volts.
INL is integral nonlinearity in volts.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5542 can be confi-
gured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors, RFB and RINV, are connected to an external op
amp to achieve this bipolar output swing, typically RFB = RINV =
28 kΩ. Table 8 shows the transfer function for this output
operating mode. Also provided on the AD5542 are a set of
Kelvin connections to the analog ground inputs.
+5V +2.5V
10µF
0.1µF
0.1µF
SERIAL
INTERFACE
RFB
VDD
CS
REFF REFS
RFB INV
DIN
SCLK
LDAC
RINV
OUT
AD5541/AD5542
DGND AGNDF AGNDS
+5V
UNIPOLAR
OUTPUT
–5V
EXTERNAL
OP AMP
Figure 24. Bipolar Output (AD5542 Only)
Table 8. Bipolar Code Table
DAC Latch Contents
MSB
LSB
Analog Output
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
+VREF × (32,767/32,768)
+VREF × (1/32,768)
0V
0111 1111 1111 1111
0000 0000 0000 0000
−VREF × (1/32,768)
−VREF × (32,768/32,768) = −VREF
Assuming a perfect reference, the worst-case bipolar output
voltage can be calculated from the following equation:
[( )(( )) ( )] VOUT-BIP =
VOUT − UNI + VOS 2 + RD
1 + 2 + RD
− VREF 1 + RD
A
where:
VOUT-BIP is the bipolar mode worst-case output.
VOUT−UNI is the unipolar mode worst-case output.
VOS is the external op amp input offset voltage.
RD is the RFB and RINV resistor matching error.
A is the op amp open-loop gain.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±VREF
output. In a single-supply application, selection of a suitable op
amp may be more difficult as the output swing of the amplifier
does not usually include the negative rail, in this case, AGND.
This can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have a very low-offset voltage (the
DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 kΩ), adds to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, hence increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance
at high frequencies is preferred because the amplifiers need to
be able to handle dynamic currents of up to ±20 mA.
REFERENCE AND GROUND
Because the input impedance is code-dependent, the reference
pin should be driven from a low impedance source. The AD5541/
AD5542 operate with a voltage reference ranging from 2 V to
VDD. References below 2 V result in reduced accuracy. The full-
scale output voltage of the DAC is determined by the reference.
Table 7 and Table 8 outline the analog output voltage or partic-
ular digital codes. For optimum performance, Kelvin sense
connections are provided on the AD5542.
If the application does not require separate force and sense
lines, tie the lines close to the package to minimize voltage
drops between the package leads and the internal die.
Rev. F | Page 12 of 20
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