EVAL-AD5780SDZ(RevC) データシートの表示（PDF） - Analog Devices
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EVAL-AD5780SDZ Datasheet PDF : 28 Pages
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Data Sheet
AD5780
Asynchronous DAC Update
In this mode, LDAC is held high while data is being clocked
into the input shift register. The DAC output is asynchronously
updated by taking LDAC low after SYNC has been taken high.
The update now occurs on the falling edge of LDAC.
Reset Function (RESET)
The AD5780 can be reset to its power-on state by two means:
either by asserting the RESET pin or by using the reset function
in the software control register (see Table 13). If the RESET pin
is not used, hardwire it to IOVCC.
Asynchronous Clear Function (CLR)
The CLR pin is an active low clear that allows the output to be
cleared to a user defined value. The 18-bit clearcode value is
programmed to the clearcode register (see Table 12). It is
necessary to maintain CLR low for a minimum amount of time
to complete the operation (see Figure 2). When the CLR signal
is returned high, the output remains at the clear value (if LDAC
is high) until a new value is loaded to the DAC register. The
output cannot be updated with a new value while the CLR pin is
low. A clear operation can also be performed by setting the CLR
bit in the software control register (see Table 13).
ON-CHIP REGISTERS
DAC Register
Table 9 outlines how data is written to and read from the DAC
register.
The following equation describes the ideal transfer function of
the DAC:
( ) VOUT =
VREFP − VREFN
218
× D + VREFN
where:
VREFN is the negative voltage applied at the VREFN input pin.
VREFP is the positive voltage applied at the VREFP input pin.
D is the 18-bit code programmed to the DAC.
Table 8. Hardware Control Pins Truth Table
LDAC CLR RESET Function
X1
X1
0
X
X1
X1
X
The AD5780 is in reset mode. The device cannot be programmed.
The AD5780 is returned to its power-on state. All registers are set to their default values.
0
0
1
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
0
1
1
The output is set according to the DAC register value.
1
0
1
The DAC register is loaded with the clearcode register value, and the output is set accordingly.
1
1
The output is set according to the DAC register value.
0
1
The output remains at the clearcode register value.
1
1
The output remains set according to the DAC register value.
0
1
The output remains at the clearcode register value.
1
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
0
1
The DAC register is loaded with the clearcode register value and the output is set accordingly.
1
1
The output remains at the clearcode register value.
0
1
The output is set according to the DAC register value.
1 X is don’t care.
Table 9. DAC Register
MSB
DB23
DB22
R/W
R/W
0
1 X is don’t care.
DB21
DB20
Register address
0
1
DB19 to DB2
DAC register data
18 bits of data
DB1
X1
LSB
DB0
X1
X
Rev. C | Page 21 of 28
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