TIMING DIAGRAMS
RESET
tRESL
Figure 3. Reset Timing Requirements
CLKx
tCLKH
tCLKL
Figure 4. CLK Switching Characteristics
(x = A, B, C, D for Individual Input Ports)
CLKA
CLKx
tCLKSKEW
tCLKH
tCLK
tCLKL
Figure 5. CLK Skew Characteristics
(x = B, C, D for Individual Input Ports)
CPUCLK
tCPUCLKH
tCPUCLKL
Figure 6. CPUCLK Switching Characteristics
SCLK
tSCLKH
tSCLKL
Figure 7. SCLK Switching Characteristics
CLKA
SYNC [3:0]
tSSYNC
tHSYNC
Figure 8. SYNC Timing Inputs
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