AD6672(Rev0) データシートの表示（PDF） - Analog Devices

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AD6672
(Rev.:Rev0)

IF Receiver

Analog Devices 

AD6672

MEMORY MAP REGISTER TABLE

All address and bit locations that are not included in Table 13 are not currently supported for this device.

Table 13. Memory Map Registers

Addr Register

(Hex) Name

Bit 7

(MSB)

Chip Configuration Registers

0x00 SPI port

0

configuration

Bit 6

LSB first

0x01 Chip ID

0x02 Chip grade

Open

Open

Transfer Register

0xFF Transfer

Open

Open

ADC Functions Registers

0x08 Power modes Open

Open

0x09 Global clock Open

Open

0x0B Clock divide Open

Open

0x0D Test mode

0x0E BIST enable

User test

mode

control

0 = con-

tinuous/

repeat

pattern

1=

single

pattern,

then 0s

Open

Open

Open

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

Soft reset 1

1

8-bit chip ID[7:0]

(AD6672 = 0xA4)

(default)

Speed grade ID

Open

00 = 250 MSPS

Soft reset LSB first

Open

Open

0

0x18

Nibbles are

mirrored so

that LSB

first mode

or MSB first

mode is set

correctly,

regardless

of shift

mode.

0xA4

Read only.

Open

Speed

grade ID

used to dif-

ferentiate

devices;

read only.

Open

Open

Open

Open

Open

Transfer 0x00

Synchro-

nously

transfers

data from

the master

shift

register to

the slave.

Open

Open

Open

Open

Open

Open

Input clock divider phase adjust

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

111 = 7 input clock cycles

Open

Internal power-down

mode

00 = normal operation

01 = full power-down

10 = standby

11 = reserved

Open

Open

Duty

cycle

stabilizer

(default)

Clock divide ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

0x01

0x00

Reset PN

long gen

Open

Reset PN

short gen

Open

Open

Output test mode

0000 = off (default)

0001 = midscale short

0010 = positive FS

0011 = negative FS

0100 = alternating checkerboard

0101 = PN long sequence

0110 = PN short sequence

0111 = one/zero word toggle

1000 = user test mode

1001 to 1110 = unused

1111 = ramp output

Reset BIST Open

sequence

0x00

BIST

enable

0x00

Determines

various

generic

modes

of chip

operation.

Clock

divide

values

other than

000 auto-

matically

cause the

duty cycle

stabilizer

to become

active.

When this

register is

set, the

test data is

placed on

the output

pins in

place of

normal

data.

Rev. 0 | Page 26 of 32

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