AD7303 データシートの表示（PDF） - Analog Devices
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AD7303 Datasheet PDF : 16 Pages
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AD7303
TIMING CHARACTERISTICS1, 2 (VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference; all specifications
TMIN to TMAX unless otherwise noted)
Parameter
Limit at TMIN, TMAX (B Version)
Units
Conditions/Comments
t1
33
t2
13
t3
13
t4
5
t5
5
t6
4.5
t7
4.5
t8
33
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC Setup Time
Data Setup Time
Data Hold Time
SYNC Hold Time
Minimum SYNC High Time
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2,
tr and tf should not exceed 1 µs on any input.
2See Figures 1 and 2.
SCLK (I)
SYNC (I)
DIN (I)
t8
t4
t5
t6
DB15
t1
t2
t3
t7
t4
DB0
Figure 1. Timing Diagram for Continuous 16-Bit Write
SCLK (I)
SYNC (I)
DIN (I)
t8
t4
t1
t2
t3
t5
t6
DB15
DB8
t5
t6
DB7
Figure 2. Timing Diagram for 2 × 8-Bit Writes
t7
DB0
REV. 0
–3–
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