AD7441BRM データシートの表示（PDF） - Analog Devices
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AD7441BRM Datasheet PDF : 15 Pages
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PRELIMINARY TECHNICAL DATA
AD7451/AD7441
tPOWERUP
THE PART BEGINS
+5
TO POWER UP
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
SCLK
A1
10
16
1
10
16
SDATA
INVALID DATA
VALID DATA
Figure 7. Exiting Power Down Mode
Although at any SCLK frequency one dummy cycle is
sufficient to power the device up and acquire VIN, it does
not necessarily mean that a full dummy cycle of 16
SCLKs must always elapse to power up the device and
acquire VIN fully; 1µs will be sufficient to power the de-
vice up and acquire the input signal.
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7451/41 when
not converting, the average power consumption of the
ADC decreases at lower throughput rates. Figure 8 shows
how, as the throughput rate is reduced, the device remains
in its power-down state longer and the average power con-
sumption reduces accordingly. It shows this for both 5V
For example, if a 5MHz SCLK frequency was applied to and 3V power supplies.
the ADC, the cycle time would be 3.2µs (i.e. 1/(5MHz) x
16). In one dummy cycle, 3.2µs, the part would be pow-
For example, if the AD7451/41 is operated in continous
ered up and VIN acquired fully. However after 1µs with a
5MHz SCLK only 5 SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the CS can be brought
sampling mode with a throughput rate of 100kSPS and an
SCLK of 18MHz and the device is placed in the power
down mode between conversions, then the power con-
sumption is calculated as follows:
high after the 10th SCLK falling edge and brought low
again after a time tQUIET to initiate the conversion.
Power dissipation during normal operation = 9mW max
When power supplies are first applied to the AD7451/41,
(for VDD = 5V).
the ADC may either power up in the power-down mode or
normal mode. Because of this, it is best to allow a dummy
cycle to elapse to ensure the part is fully powered up be-
fore attempting a valid conversion. Likewise, if the user
wishes the part to power up in power-down mode, then the
If the power up time is 1 dummy cycle i.e. 1µsec, and the
remaining conversion time is another cycle i.e. 1µsec, then
the AD7451/41 can be said to dissipate 9mW for 2µsec
during each conversion cycle.
dummy cycle may be used to ensure the device is in
power-down by executing a cycle such as that shown in
If the throughput rate = 100kSPS then the cycle time =
Figure 6.
10µsec and the average power dissipated during each cycle
is:
Once supplies are applied to the AD7451/41, the power
(2/10) x 9mW = 1.8mW
up time is the same as that when powering up from the
power-down mode. It takes approximately 1µs to power
For the same scenario, if VDD = 3V, the power dissipation
during normal operation is 3.75mW max.
up fully if the part powers up in normal mode. It is not
The AD7450 can now be said to dissipate 3.75mW for
necessary to wait 1µs before executing a dummy cycle to
2µsec* during each conversion cycle.
ensure the desired mode of operation. Instead, the dummy The average power dissipated during each cycle with a
cycle can occur directly after power is supplied to the
throughput rate of 100kSPS is therefore:
ADC. If the first valid conversion is then performed di-
(2/10) x 3.75mW = 0.75mW
rectly after the dummy conversion, care must be taken to
This is how the power numbers in Figure 8 are calculated.
ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-
down mode, the part will return to track upon the first
SCLK edge applied after the falling edge of CS. How-
ever, when the ADC powers up initially after supplies are
applied, the track and hold will already be in track. This
means if (assuming one has the facility to monitor the
ADC supply current) the ADC powers up in the desired
mode of operation and thus a dummy cycle is not required
to change mode, then neither is a dummy cycle required
to place the track and hold into track.
TBD
Figure 8. Power vs. Throughput rate for the
Power Down Mode
For throughput rates above 320kSPS, it is recommended
that for optimum power performance, the serial clock
frequency is reduced.
REV. PrC
–15–
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