AD8159 データシートの表示（PDF） - Analog Devices

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AD8159

3.2 Gbps Quad Buffer Mux/Demux

Analog Devices 

AD8159

DEVICE UNDER TEST

A

C

50Ω CABLE

B

AD8159

DATA OUT

PATTERN

GENERATOR

A

50Ω CABLE

50Ω CABLE

C

B

AD8159

TEST BACKPLANE

DC-COUPLED

A

EVALUATION BOARD

C

50Ω

B

DC-COUPLED

A

EVALUATION BOARD

C

B

50Ω

NOTES

1. SINGLE-ENDED REPRESENTATION

Figure 34. Equalization Test Circuit

Note: Test Circuit Used for Figure 19 and Figure 20

HIGH SPEED

50Ω

REAL-TIME

OSCILLOSCOPE

50Ω CABLE

50Ω

50Ω

50Ω CABLE

DATA OUT

A

50Ω CABLE

PATTERN

GENERATOR

C

B

AD8159

AC-COUPLED

A

EVALUATION BOARD

C

50Ω

B

50Ω

NOTES

1. SINGLE-ENDED REPRESENTATION

Figure 35. Random Jitter Test Circuit

Note: Test Circuit Used for Figure 24

HIGH SPEED

SAMPLING

OSCILLOSCOPE

50Ω

Rev. A | Page 14 of 24

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