AD8328ACP-REEL7 データシートの表示（PDF） - Analog Devices
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AD8328ACP-REEL7 Datasheet PDF : 20 Pages
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VCC
10µF
ZIN = 150Ω
VIN+
0.1µF
165Ω
VIN–
0.1µF
1kΩ
DATEN
1kΩ
SDATA
1kΩ
CLK
1kΩ
TXEN
1kΩ
SLEEP
AD8328
AD8328
1 GND QSOP GND 20
2 VCC
3 GND
VCC 19
TXEN 18
4 GND
RAMP 17
5 VIN+
6
7
VIN–
GND
VOUT+ 16
VOUT– 15
14
BYP
8 DATEN
NC 13
9 SDATA
12
SLEEP
10 CLK
GND 11
0.1μF
0.1μF
0.1μF
TO DIPLEXER
ZIN = 75Ω
TOKO 458PT-1087
Figure 20. Typical Application Circuit
Table 6. Adjacent Channel Power
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
Adjacent Channel Symbol Rate (kSym/s)
160
320
640
1280
−58
−60
−63
−66
−58
−59
−60
−64
−60
−58
−59
−61
−62
−60
−59
−60
−64
−62
−60
−59
−66
−65
−62
−61
2560
−66
−66
−64
−61
−60
−59
5120
−64
−65
−65
−63
−61
−60
The output impedance of the AD8328 is 300 Ω, regardless
of whether the amplifier is in transmit enable or transmit
disable mode. This, when combined with a 2:1 voltage ratio
(4:1 impedance ratio) transformer, eliminates the need for
external back termination resistors. If the output signal is being
evaluated using standard 50 Ω test equipment, a minimum loss
75 Ω to 50 Ω pad must be used to provide the test circuit with
the proper impedance match. The AD8328 evaluation board
provides a convenient means to implement a matching attenuator.
Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω
resistor in the R16 placeholder allows testing on a 50 Ω system.
When using a matching attenuator, it should be noted that there
is a 5.7 dB of power loss (7.5 dB voltage) through the network.
POWER SUPPLY
The 5 V supply should be delivered to each of the VCC pins via a
low impedance power bus to ensure that each pin is at the same
potential. The power bus should be decoupled to ground using
a 10 μF tantalum capacitor located close to the AD8328. In
addition to the 10 μF capacitor, each VCC pin should be individually
decoupled to ground with ceramic chip capacitors located close
to the pins. The bypass pin, BYP, should also be decoupled. The
PCB should have a low impedance ground plane covering all
unused portions of the board, except in areas of the board
where input and output traces are in close proximity to the
AD8328 and the output transformer. All AD8328 ground pins
must be connected to the ground plane to ensure proper
grounding of all internal nodes.
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short minimizes parasitic capacitance and inductance. This is
most critical between the outputs of the AD8328 and the 2:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the
input and output traces should be adequately spaced to
minimize coupling (crosstalk) through the board. Following
these guidelines optimizes the overall performance of the
AD8328 in all applications.
Rev. A | Page 11 of 20
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