AD8328ACP-REEL7 データシートの表示（PDF） - Analog Devices
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AD8328ACP-REEL7 Datasheet PDF : 20 Pages
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD8328
GND 1
20 GND
VCC 2
GND 3
19 VCC
18 TXEN
GND
VIN+
VIN–
GND
4
17 RAMP
AD8328
5 TOP VIEW 16 VOUT+
6 (Not to Scale) 15 VOUT–
7
14 BYP
DATEN 8
13 NC
SDATA 9
12 SLEEP
CLK 10
11 GND
NC = NO CONNECT
Figure 5. 20-Lead QSOP Pin Configuration
20 19 18 17 16
GND 1
GND 2
VIN+ 3
VIN– 4
GND 5
AD8328
TOP VIEW
(Not to Scale)
15 RAMP
14 VOUT+
13 VOUT–
12 BYP
11 NC
6 7 8 9 10
Figure 6. 20-Lead LFCSP Pin Configuration
Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions
Pin No. Pin No.
20-Lead 20-Lead
QSOP LFCSP Mnemonic Description
1, 3, 4, 7, 1, 2, 5, 9, GND
11, 20 18, 19
Common External Ground Reference.
2, 19
17, 20
VCC
Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.
5
3
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
6
4
VIN−
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
8
6
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)
and simultaneously inhibits serial data transfer into the register.
A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and
simultaneously enables the register for serial data load.
9
7
SDATA
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the
internal register with the most significant bit (MSB) first.
10
8
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave register.
A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
12
10
SLEEP
Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.
A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part.
13
11
NC
No Connect.
14
12
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).
15
13
VOUT−
Negative Output Signal
16
14
VOUT+
Positive Output Signal
17
15
RAMP
External RAMP Capacitor (Optional)
18
16
TXEN
Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.
Rev. A | Page 7 of 20
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