AD9142 データシートの表示（PDF） - Analog Devices

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AD9142

Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices 

AD9142

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Input Signal Power Detection and Protection........................ 30

Applications....................................................................................... 1

Transmit Enable Function......................................................... 31

General Description ......................................................................... 1

Digital Function Configuration ............................................... 31

Product Highlights ........................................................................... 1

Multidevice Synchronization and Fixed Latency....................... 32

Revision History ............................................................................... 3

Very Small Inherent Latency Variation ................................... 32

Functional Block Diagram .............................................................. 4

Further Reducing the Latency Variation................................. 32

Specifications..................................................................................... 5

Synchronization Implementation ............................................ 33

DC Specifications ......................................................................... 5

Synchronization Procedures ..................................................... 33

Digital Specifications ................................................................... 6

Interrupt Request Operation ........................................................ 34

DAC Latency Specifications........................................................ 7

Interrupt Working Mechanism ................................................ 34

Latency Variation Specifications ................................................ 7

Interrupt Service Routine.......................................................... 34

AC Specifications.......................................................................... 7

Temperature Sensor ....................................................................... 35

Operating Speed Specifications .................................................. 8

DAC Input Clock Configurations ................................................ 36

Absolute Maximum Ratings ....................................................... 9

Driving the DACCLK and REFCLK Inputs ........................... 36

Thermal Resistance ...................................................................... 9

Direct Clocking .......................................................................... 36

ESD Caution.................................................................................. 9

Clock Multiplication .................................................................. 36

Pin Configuration and Function Descriptions........................... 10

PLL Settings ................................................................................ 37

Typical Performance Characteristics ........................................... 12

Configuring the VCO Tuning Band ........................................ 37

Terminology .................................................................................... 17

Automatic VCO Band Select .................................................... 37

Serial Port Operation ..................................................................... 18

Manual VCO Band Select ......................................................... 37

Data Format ................................................................................ 18

Analog Outputs............................................................................... 38

Serial Port Pin Descriptions...................................................... 18

Transmit DAC Operation.......................................................... 38

Serial Port Options ..................................................................... 18

Interfacing to Modulators ......................................................... 39

Data Interface .................................................................................. 20

Reducing LO Leakage and Unwanted Sidebands .................. 40

LVDS Input Data Ports .............................................................. 20

Example Start-Up Routine ............................................................ 41

Word Interface Mode ................................................................. 20

Device Configuration Register Map and Description............... 42

Byte Interface Mode ................................................................... 20

SPI Configure Register .............................................................. 44

Data Interface Configuration Options .................................... 20

Power-Down Control Register ................................................. 44

Interface Delay Line ................................................................... 22

Interrupt Enable0 Register ........................................................ 44

FIFO Operation .............................................................................. 23

Interrupt Enable1 Register ........................................................ 44

Resetting the FIFO ..................................................................... 24

Interrupt Flag0 Register............................................................. 45

Serial Port Initiated FIFO Reset ............................................... 24

Interrupt Flag1 Register............................................................. 45

Frame Initiated FIFO Reset....................................................... 24

Interrupt Select0 Register.......................................................... 45

Digital Datapath.............................................................................. 26

Interrupt Select1 Register.......................................................... 46

Interpolation Filters ................................................................... 26

DAC Clock Receiver Control Register .................................... 46

Digital Modulation..................................................................... 28

Ref Clock Receiver Control Register ....................................... 46

Datapath Configuration ............................................................ 29

PLL Control Register ................................................................. 47

Digital Quadrature Gain and Phase Adjustment ................... 29

PLL Control Register ................................................................. 47

DC Offset Adjustment ............................................................... 29

PLL Control Register ................................................................. 47

Inverse Sinc Filter ....................................................................... 30

PLL Status Register..................................................................... 48

Rev. 0 | Page 2 of 64

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