AD9219(RevE) データシートの表示（PDF） - Analog Devices

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AD9219
(Rev.:RevE)

Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC

Analog Devices 

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AVDD 1

AVDD 2

VIN – D 3

VIN + D 4

AVDD 5

AVDD 6

CLK– 7

CLK+ 8

AVDD 9

AVDD 10

DRGND 11

DRVDD 12

PIN 1

INDICATOR

EXPOSED PADDLE, PIN 0

(BOTTOM OF PACKAGE)

AD9219

TOP VIEW

36 AVDD

35 AVDD

34 VIN – A

33 VIN + A

32 AVDD

31 PDWN

30 CSB

29 SDIO/ODM

28 SCLK/DTP

27 AVDD

26 DRGND

25 DRVDD

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.

Figure 5. 48-Lead LFCSP Pin Configuration, Top View

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

0

AGND

1, 2, 5, 6, 9, 10, 27, 32,

35, 36, 39, 45, 46

AVDD

11, 26

DRGND

12, 25

DRVDD

3

VIN − D

4

VIN + D

7

CLK−

8

CLK+

13

D−D

14

D+D

15

D−C

16

D+C

17

D−B

18

D+B

19

D−A

20

D+A

21

FCO−

22

FCO+

23

DCO−

24

DCO+

28

SCLK/DTP

29

SDIO/ODM

Description

Analog Ground (Exposed Paddle)

1.8 V Analog Supply

Digital Output Driver Ground

1.8 V Digital Output Driver Supply

ADC D Analog Input Complement

ADC D Analog Input True

Input Clock Complement

Input Clock True

ADC D Digital Output Complement

ADC D Digital Output True

ADC C Digital Output Complement

ADC C Digital Output True

ADC B Digital Output Complement

ADC B Digital Output True

ADC A Digital Output Complement

ADC A Digital Output True

Frame Clock Output Complement

Frame Clock Output True

Data Clock Output Complement

Data Clock Output True

Serial Clock/Digital Test Pattern

Serial Data IO/Output Driver Mode

Rev. E | Page 11 of 56

AD9219

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