AD9233-105EB データシートの表示（PDF） - Analog Devices
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AD9233-105EB Datasheet PDF : 44 Pages
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AD9233
Table 9. Reference Configuration Summary
Selected Mode
SENSE Voltage
External Reference
AVDD
Internal Fixed Reference
VREF
Programmable Reference
0.2 V to VREF
Internal Fixed Reference
AGND to 0.2 V
Resulting VREF (V)
N/A
0.5
0.5 × (1 + R2/R1) (See Figure 43)
1.0
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF
2.0
0
–0.25
–0.50
VREF = 0.5V
VREF = 1V
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
Figure 44. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 45 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
10
8
VREF = 0.5V
6
VREF = 1V
4
2
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 45. Typical VREF Drift
When the SENSE pin is tied to the AVDD pin, the internal
reference is disabled, allowing the use of an external reference.
An internal resistor divider loads the external reference with an
equivalent 6 kΩ load (see Figure 11). In addition, an internal
buffer generates the positive and negative full-scale references
for the ADC core. Therefore, the external reference must be
limited to a maximum of 1 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9233 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.
Clock Input Options
The AD9233 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 46 shows one preferred method for clocking the
AD9233. A low jitter clock source is converted from single-
ended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9233 to approximately
0.8 V p-p differential. This helps prevent the large voltage
swings of the clock from feeding through to other portions of
the AD9233 while preserving the fast rise and fall times of the
signal, which are critical to a low jitter performance.
CLOCK
INPUT
0.1µF
MIN-CIRCUITS
ADT1–1WT, 1:1Z
XFMR 0.1µF
50Ω 100Ω
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSMS2812
CLK+
ADC
AD9233
CLK–
Figure 46. Transformer Coupled Differential Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 47. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers
excellent jitter performance.
CLOCK
INPUT
CLOCK
INPUT
50Ω*
0.1µF
CLK
AD951x
0.1µF PECL DRIVER
CLK
50Ω*
240Ω
0.1µF
100Ω
0.1µF
240Ω
CLK+
ADC
AD9233
CLK–
Rev. A | Page 18 of 44
*50Ω RESISTORS ARE OPTIONAL
Figure 47. Differential PECL Sample Clock
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