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AD9258BCPZ-80 データシートの表示(PDF) - Analog Devices

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AD9258BCPZ-80 Datasheet PDF : 44 Pages
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AD9258
Parameter1
WORST OTHER (HARMONIC OR SPUR)
Without Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
With On-Chip Dither
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE SFDR WITHOUT DITHER
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ),172 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH
AD9258BCPZ-80
Temp Min Typ Max
25°C
−100
25°C
−100 −96
Full
−96
25°C
−97
25°C
−95
25°C
−109
25°C
−105 −96
Full
−96
25°C
−106
25°C
−102
25°C
93
25°C
81
Full
−95
25°C
650
AD9258BCPZ-105
Min Typ Max
−100
−99 −94
−94
−97
−95
−107
−106 −95
−95
−104
−104
92
80
−95
650
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
AD9258BCPZ-125
Min Typ Max
−99
−98 −94
−94
−97
−95
−107
−105 −95
−95
−103
−97
90
82
−95
650
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
0.3
AGND
0.9
−100
−100
8
CMOS/LVDS/LVPECL
0.9
3.6
AVDD
1.4
+100
+100
4
10
12
AGND
1.2
AGND
−100
−100
12
CMOS
0.9
1
16
AVDD
AVDD
0.6
+100
+100
20
Unit
V
V p-p
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
Rev. A | Page 7 of 44

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