AD9510(RevB) データシートの表示（PDF） - Analog Devices

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AD9510
(Rev.:RevB)

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

AD9510

Data Sheet

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

PIN 1

INDICATOR

0.60

MAX

0.60 MAX

49

48

8.85

8.75 SQ

8.65

0.50

BSC

EXPOSED

PAD

PIN 1

64

1

INDICATOR

*4.85

4.70 SQ

4.55

1.00 12° MAX

0.85

0.80

SEATING

PLANE

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

33

32

17 16

BOTTOM VIEW

7.50 REF

0.25 MIN

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

EXCEPT FOR EXPOSED PAD DIMENSION

Figure 59. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

AD9510BCPZ

AD9510BCPZ-REEL7

AD9510/PCBZ

AD9510-VCO/PCBZ

Temperature Range

−40°C to +85°C

−40°C to +85°C

1 Z = RoHS compliant part.

Package Description

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board Without VCO or VCXO or Loop Filter

Evaluation Board With 245.76 MHz VCXO, Loop Filter

Package Option

CP-64-1

CP-64-1

©2005–2013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D05046-0-9/13(B)

Rev. B | Page 56 of 56

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