AD9515(Rev0) データシートの表示（PDF） - Analog Devices

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AD9515
(Rev.:Rev0)

1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

Analog Devices 

TIMING DIAGRAMS

CLK

tCLK

tPECL

tLVDS

tCMOS

Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode

DIFFERENTIAL

80%

LVPECL

20%

tRP

tFP

Figure 3. LVPECL Timing, Differential

AD9515

DIFFERENTIAL

80%

20%

LVDS

tRL

tFL

Figure 4. LVDS Timing, Differential

SINGLE-ENDED

80%

20%

CMOS

3pF LOAD

tRC

tFC

Figure 5. CMOS Timing, Single-Ended, 3 pF Load

Rev. 0 | Page 11 of 28

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